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Jason2866Jason2866
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add c2
1 parent fbfcb80 commit 81f63a9

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-70
lines changed

‎cores/esp32/Esp.cpp

Lines changed: 94 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,9 @@ extern "C" {
4848
#include "esp32s3/rom/spi_flash.h"
4949
#include "soc/efuse_reg.h"
5050
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32s3 is located at 0x0000
51+
#elif CONFIG_IDF_TARGET_ESP32C2
52+
#include "esp32c2/rom/spi_flash.h"
53+
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c2 is located at 0x0000
5154
#elif CONFIG_IDF_TARGET_ESP32C3
5255
#include "esp32c3/rom/spi_flash.h"
5356
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c3 is located at 0x0000
@@ -366,7 +369,7 @@ FlashMode_t EspClass::getFlashChipMode(void)
366369
#if CONFIG_IDF_TARGET_ESP32S2
367370
uint32_t spi_ctrl = REG_READ(PERIPHS_SPI_FLASH_CTRL);
368371
#else
369-
#if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
372+
#if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
370373
uint32_t spi_ctrl = REG_READ(DR_REG_SPI0_BASE + 0x8);
371374
#else
372375
uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
@@ -391,36 +394,106 @@ FlashMode_t EspClass::getFlashChipMode(void)
391394

392395
uint32_t EspClass::magicFlashChipSize(uint8_t byte)
393396
{
397+
/*
398+
FLASH_SIZES = {
399+
"1MB": 0x00,
400+
"2MB": 0x10,
401+
"4MB": 0x20,
402+
"8MB": 0x30,
403+
"16MB": 0x40,
404+
"32MB": 0x50,
405+
"64MB": 0x60,
406+
"128MB": 0x70,
407+
}
408+
*/
394409
switch(byte & 0x0F) {
395-
case 0x0: // 8 MBit (1MB)
396-
return (1_MB);
397-
case 0x1: // 16 MBit (2MB)
398-
return (2_MB);
399-
case 0x2: // 32 MBit (4MB)
400-
return (4_MB);
401-
case 0x3: // 64 MBit (8MB)
402-
return (8_MB);
403-
case 0x4: // 128 MBit (16MB)
404-
return (16_MB);
405-
default: // fail?
410+
case 0x0: return (1_MB); // 8 MBit (1MB)
411+
case 0x1: return (2_MB); // 16 MBit (2MB)
412+
case 0x2: return (4_MB); // 32 MBit (4MB)
413+
case 0x3: return (8_MB); // 64 MBit (8MB)
414+
case 0x4: return (16_MB); // 128 MBit (16MB)
415+
case 0x5: return (32_MB); // 256 MBit (32MB)
416+
case 0x6: return (64_MB); // 512 MBit (64MB)
417+
case 0x7: return (128_MB); // 1 GBit (128MB)
418+
default: // fail?
406419
return 0;
407420
}
408421
}
409422

410423
uint32_t EspClass::magicFlashChipSpeed(uint8_t byte)
411424
{
425+
#if CONFIG_IDF_TARGET_ESP32C2
426+
/*
427+
FLASH_FREQUENCY = {
428+
"60m": 0xF,
429+
"30m": 0x0,
430+
"20m": 0x1,
431+
"15m": 0x2,
432+
}
433+
*/
412434
switch(byte & 0x0F) {
413-
case 0x0: // 40 MHz
414-
return (40_MHz);
415-
case 0x1: // 26 MHz
416-
return (26_MHz);
417-
case 0x2: // 20 MHz
418-
return (20_MHz);
419-
case 0xf: // 80 MHz
420-
return (80_MHz);
421-
default: // fail?
435+
case 0xF: return (60_MHz);
436+
case 0x0: return (30_MHz);
437+
case 0x1: return (20_MHz);
438+
case 0x2: return (15_MHz);
439+
default: // fail?
422440
return 0;
423441
}
442+
443+
444+
#elif CONFIG_IDF_TARGET_ESP32C6
445+
/*
446+
FLASH_FREQUENCY = {
447+
"80m": 0x0, # workaround for wrong mspi HS div value in ROM
448+
"40m": 0x0,
449+
"20m": 0x2,
450+
}
451+
*/
452+
switch(byte & 0x0F) {
453+
case 0x0: return (80_MHz);
454+
case 0x2: return (20_MHz);
455+
default: // fail?
456+
return 0;
457+
}
458+
459+
#elif CONFIG_IDF_TARGET_ESP32H2
460+
461+
/*
462+
FLASH_FREQUENCY = {
463+
"48m": 0xF,
464+
"24m": 0x0,
465+
"16m": 0x1,
466+
"12m": 0x2,
467+
}
468+
*/
469+
switch(byte & 0x0F) {
470+
case 0xF: return (48_MHz);
471+
case 0x0: return (24_MHz);
472+
case 0x1: return (16_MHz);
473+
case 0x2: return (12_MHz);
474+
default: // fail?
475+
return 0;
476+
}
477+
478+
479+
#else
480+
/*
481+
FLASH_FREQUENCY = {
482+
"80m": 0xF,
483+
"40m": 0x0,
484+
"26m": 0x1,
485+
"20m": 0x2,
486+
}
487+
*/
488+
switch(byte & 0x0F) {
489+
case 0xF: return (80_MHz);
490+
case 0x0: return (40_MHz);
491+
case 0x1: return (26_MHz);
492+
case 0x2: return (20_MHz);
493+
default: // fail?
494+
return 0;
495+
}
496+
#endif
424497
}
425498

426499
FlashMode_t EspClass::magicFlashChipMode(uint8_t byte)

‎cores/esp32/HardwareSerial.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,8 @@ typedef enum {
118118
#define SOC_RX0 (gpio_num_t)3
119119
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
120120
#define SOC_RX0 (gpio_num_t)44
121+
#elif CONFIG_IDF_TARGET_ESP32C2
122+
#define SOC_RX0 (gpio_num_t)19
121123
#elif CONFIG_IDF_TARGET_ESP32C3
122124
#define SOC_RX0 (gpio_num_t)20
123125
#elif CONFIG_IDF_TARGET_ESP32C6
@@ -132,6 +134,8 @@ typedef enum {
132134
#define SOC_TX0 (gpio_num_t)1
133135
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
134136
#define SOC_TX0 (gpio_num_t)43
137+
#elif CONFIG_IDF_TARGET_ESP32C2
138+
#define SOC_TX0 (gpio_num_t)20
135139
#elif CONFIG_IDF_TARGET_ESP32C3
136140
#define SOC_TX0 (gpio_num_t)21
137141
#elif CONFIG_IDF_TARGET_ESP32C6
@@ -149,6 +153,8 @@ typedef enum {
149153
#define RX1 (gpio_num_t)26
150154
#elif CONFIG_IDF_TARGET_ESP32S2
151155
#define RX1 (gpio_num_t)4
156+
#elif CONFIG_IDF_TARGET_ESP32C2
157+
#define RX1 (gpio_num_t)9
152158
#elif CONFIG_IDF_TARGET_ESP32C3
153159
#define RX1 (gpio_num_t)18
154160
#elif CONFIG_IDF_TARGET_ESP32S3
@@ -165,6 +171,8 @@ typedef enum {
165171
#define TX1 (gpio_num_t)27
166172
#elif CONFIG_IDF_TARGET_ESP32S2
167173
#define TX1 (gpio_num_t)5
174+
#elif CONFIG_IDF_TARGET_ESP32C2
175+
#define TX1 (gpio_num_t)10
168176
#elif CONFIG_IDF_TARGET_ESP32C3
169177
#define TX1 (gpio_num_t)19
170178
#elif CONFIG_IDF_TARGET_ESP32S3

‎cores/esp32/esp32-hal-cpu.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
#include "esp_attr.h"
2020
#include "esp_log.h"
2121
#include "soc/rtc.h"
22-
#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
22+
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
2323
#include "soc/rtc_cntl_reg.h"
2424
#include "soc/apb_ctrl_reg.h"
2525
#endif
@@ -38,6 +38,8 @@
3838
#elif CONFIG_IDF_TARGET_ESP32S3
3939
#include "freertos/xtensa_timer.h"
4040
#include "esp32s3/rom/rtc.h"
41+
#elif CONFIG_IDF_TARGET_ESP32C2
42+
#include "esp32c2/rom/rtc.h"
4143
#elif CONFIG_IDF_TARGET_ESP32C3
4244
#include "esp32c3/rom/rtc.h"
4345
#elif CONFIG_IDF_TARGET_ESP32C6
@@ -153,7 +155,7 @@ bool removeApbChangeCallback(void * arg, apb_change_cb_t cb){
153155
}
154156

155157
static uint32_t calculateApb(rtc_cpu_freq_config_t * conf){
156-
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
158+
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
157159
return APB_CLK_FREQ;
158160
#else
159161
if(conf->freq_mhz >= 80){
@@ -228,7 +230,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
228230
}
229231
//Make the frequency change
230232
rtc_clk_cpu_freq_set_config_fast(&conf);
231-
#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
233+
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
232234
if(capb != apb){
233235
//Update REF_TICK (uncomment if REF_TICK is different than 1MHz)
234236
//if(conf.freq_mhz < 80){
@@ -241,7 +243,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
241243
}
242244
#endif
243245
//Update FreeRTOS Tick Divisor
244-
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
246+
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
245247

246248
#elif CONFIG_IDF_TARGET_ESP32S3
247249

‎cores/esp32/esp32-hal-i2c-slave.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ static inline void i2c_ll_stretch_clr(i2c_dev_t *hw)
168168

169169
static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
170170
{
171-
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
171+
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
172172
return hw->sr.slave_addressed;
173173
#else
174174
return hw->status_reg.slave_addressed;
@@ -177,7 +177,7 @@ static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
177177

178178
static inline bool i2c_ll_slave_rw(i2c_dev_t *hw)//not exposed by hal_ll
179179
{
180-
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
180+
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
181181
return hw->sr.slave_rw;
182182
#else
183183
return hw->status_reg.slave_rw;

‎cores/esp32/esp32-hal-matrix.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,8 @@
2424
#include "esp32s2/rom/gpio.h"
2525
#elif CONFIG_IDF_TARGET_ESP32S3
2626
#include "esp32s3/rom/gpio.h"
27+
#elif CONFIG_IDF_TARGET_ESP32C2
28+
#include "esp32c2/rom/gpio.h"
2729
#elif CONFIG_IDF_TARGET_ESP32C3
2830
#include "esp32c3/rom/gpio.h"
2931
#elif CONFIG_IDF_TARGET_ESP32C6

‎cores/esp32/esp32-hal-misc.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
#endif //CONFIG_BT_ENABLED
3030
#include <sys/time.h>
3131
#include "soc/rtc.h"
32-
#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
32+
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
3333
#include "soc/rtc_cntl_reg.h"
3434
#include "soc/apb_ctrl_reg.h"
3535
#endif
@@ -45,6 +45,8 @@
4545
#include "esp32s2/rom/rtc.h"
4646
#elif CONFIG_IDF_TARGET_ESP32S3
4747
#include "esp32s3/rom/rtc.h"
48+
#elif CONFIG_IDF_TARGET_ESP32C2
49+
#include "esp32c2/rom/rtc.h"
4850
#elif CONFIG_IDF_TARGET_ESP32C3
4951
#include "esp32c3/rom/rtc.h"
5052
#elif CONFIG_IDF_TARGET_ESP32C6

‎cores/esp32/esp32-hal-rgb-led.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,6 @@
1+
#include "soc/soc_caps.h"
2+
#if SOC_RMT_SUPPORTED
3+
14
#include "esp32-hal-rgb-led.h"
25

36

@@ -35,3 +38,5 @@ void neopixelWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue
3538
}
3639
rmtWrite(pin, led_data, RMT_SYMBOLS_OF(led_data), RMT_WAIT_FOR_EVER);
3740
}
41+
42+
#endif /* SOC_RMT_SUPPORTED */

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