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Commits on Feb 27, 2018

• Merge branch 'master' of github.com:azonenberg/yosys

  azonenberg

  committed
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• Merge branch 'master' of https://github.com/cliffordwolf/yosys

  azonenberg

  committed
  0ae85c7

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• Add -lz for verific builds

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  cliffordwolf

  committed
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Commits on Feb 26, 2018

• Add handling of verific OPER_REDUCE_NOR

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  cliffordwolf

  committed
  b6fbeb0

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• Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR

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  cliffordwolf

  committed
  2aeb4d4

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• Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX

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  cliffordwolf

  committed
  9cd9f5f

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• Add "SVA syntax cheat sheet" comment to verificsva.cc

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  cliffordwolf

  committed
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• Add $dlatchsr support to clk2fflogic

  cliffordwolf

  committed
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• Small fixes and improvements in $allconst/$allseq handling

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  cliffordwolf

  committed
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• Fix opt_rmdff handling of $dlatchsr

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  cliffordwolf

  committed
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Commits on Feb 23, 2018

• Merge branch 'forall'

  cliffordwolf

  committed
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• Add smtbmc support for exist-forall problems

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  cliffordwolf

  committed
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• Add $allconst and $allseq cell types

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  cliffordwolf

  committed
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• Merge branch 'master' of https://github.com/cliffordwolf/yosys

  

  Andrew Zonenberg

  committed
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Commits on Feb 22, 2018

• Add Verific SVA support for ranges in repetition operator

  cliffordwolf

  committed
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Commits on Feb 21, 2018

• Add support for SVA throughout via Verific

  cliffordwolf

  committed
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Commits on Feb 20, 2018

• Add support for mockup clock signals in yosys-smtbmc vcd output

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  cliffordwolf

  committed
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Commits on Feb 19, 2018

• Merge pull request #507 from cr1901/msys2

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  cliffordwolf

  authored
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• Improve msys2 flags for building abc.

  cr1901

  committed
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Commits on Feb 18, 2018

• Add support for SVA sequence concatenation ranges via verific

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  cliffordwolf

  committed
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• Add support for SVA until statements via Verific

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  cliffordwolf

  committed
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• Move Verific SVA importer to extra C++ source file

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  cliffordwolf

  committed
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• Merge Verific SVA preprocessor and SVA importer

  cliffordwolf

  committed
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Commits on Feb 16, 2018

• Merge branch 'master' of github.com:cliffordwolf/yosys

  cliffordwolf

  committed
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Commits on Feb 15, 2018

• Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction)

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  cliffordwolf

  committed
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• Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF

  cliffordwolf

  committed
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Commits on Feb 13, 2018

• Fixed yosys-config for binary distributions with Verific

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  cliffordwolf

  committed
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• Recognize stand-alone obj pattern even when it contains a slash

  cliffordwolf

  committed
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Commits on Feb 8, 2018

• Fix handling of zero-length cell connections in SMT2 back-end

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  cliffordwolf

  committed
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Commits on Feb 3, 2018

• Merge branch 'master' of github.com:cliffordwolf/yosys

  cliffordwolf

  committed
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• Do not create deep backtraces unless in ENABLE_DEBUG mode

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  cliffordwolf

  committed
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• Merge pull request #488 from azonenberg/for_clifford

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  cliffordwolf

  authored
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• Fixed gcc 7.2 "statement will never be executed" warning

  cliffordwolf

  committed
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Commits on Feb 1, 2018

• Fix single-bit $stable handling in verific front-end

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  cliffordwolf

  committed
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Commits on Jan 31, 2018

• Add Verific attribute handling for assert/assume/cover/live/fair cells

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  cliffordwolf

  committed
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