Skip to content

Commit f5aff0e

Browse files
committed
Fix SPI issue for SPI1
1 parent cf5bae1 commit f5aff0e

File tree

3 files changed

+7
-3
lines changed

3 files changed

+7
-3
lines changed

platforms/arm/k66/clockless_block_arm_k66.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33

44
//
55
// unmodified from k20 code
6+
// TODO: check if PORTB can be used from bit 16-23 (byte 3)? -> 24-Way Parallel?
67
//
78

89
// Definition for a single channel clockless controller for the k20 family of chips, like that used in the teensy 3.0/3.1

platforms/arm/k66/fastpin_arm_k66.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,6 @@ _DEFPIN_ARM(60, 2, E); _DEFPIN_ARM(61, 3, E); _DEFPIN_ARM(62, 4, E); _DEFPIN_
112112

113113
#define SPI_DATA 11
114114
#define SPI_CLOCK 13
115-
#define SPI1 (*(SPI_t *)0x4002D000)
116115

117116
#define SPI2_DATA 7
118117
#define SPI2_CLOCK 14

platforms/arm/k66/fastspi_arm_k66.h

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,11 @@
22
#define __INC_FASTSPI_ARM_H
33

44
//
5-
// unmodified from k20 code
5+
// copied from k20 code
6+
// changed SPI1 define to KINETISK_SPI1
7+
// TODO: add third alternative MOSI pin (28) and CLOCK pin (27)
8+
// TODO: add alternative pins for SPI1
9+
// TODO: add SPI2 output
610
//
711

812
FASTLED_NAMESPACE_BEGIN
@@ -264,7 +268,7 @@ class ARMHardwareSPIOutput {
264268
SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;
265269
SPIX.CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1);
266270
}
267-
} else if((SPI_t*)pSPIX == &SPI1) {
271+
} else if((SPI_t*)pSPIX == &KINETISK_SPI1) {
268272
if (!(sim6 & SIM_SCGC6_SPI1)) {
269273
//serial_print("init1\n");
270274
SIM_SCGC6 = sim6 | SIM_SCGC6_SPI1;

0 commit comments

Comments
 (0)