Correct verilog code source

Author: damofthemoon

sim/test/fifo_unit_test.sv

@@ -1,5 +1,4 @@
 `include "svut_h.sv"
-`include "../../src/vlog/fifo.v"
 `timescale 1 ns / 1 ps
 
 module fifo_unit_test;
@@ -9,12 +8,16 @@ module fifo_unit_test;
     parameter DSIZE = 8;
     parameter ASIZE = 4;
 
-    [DSIZE-1:0] wdata;
-    winc; wclk; wrst_n;
-    rinc; rclk; rrst_n;
-    [DSIZE-1:0] rdata;
-    wfull;
-    rempty;
+    wire [DSIZE-1:0] wdata;
+    wire winc;
+    wire wclk;
+    wire wrst_n;
+    wire rinc;
+    wire rclk;
+    wire rrst_n;
+    wire [DSIZE-1:0] rdata;
+    wire wfull;
+    wire rempty;
 
     fifo 
     #(
@@ -24,7 +27,11 @@ module fifo_unit_test;
     dut 
     (
     wdata,
+    winc,
+    wclk,
     wrst_n,
+    rinc,
+    rclk,
     rrst_n,
     rdata,
     wfull,

sim/test/files.f

@@ -1,6 +1,6 @@
-fifo_2mem.v
-fifo.v
-rptr_empty.v
-sync_r2w.v
-sync_w2r.v
-wptr_full.v
+../../src/vlog/fifo.v
+../../src/vlog/fifo_2mem.v
+../../src/vlog/rptr_empty.v
+../../src/vlog/sync_r2w.v
+../../src/vlog/sync_w2r.v
+../../src/vlog/wptr_full.v

src/vlog/fifo.v

@@ -18,13 +18,18 @@
 `default_nettype none
 
 module fifo
+    
     #(
     parameter DSIZE = 8,
     parameter ASIZE = 4
     )(
     input  [DSIZE-1:0] wdata,
-    input winc, wclk, wrst_n,
-    input rinc, rclk, rrst_n,
+    input winc,
+    input wclk,
+    input wrst_n,
+    input rinc,
+    input rclk,
+    input rrst_n,
     output [DSIZE-1:0] rdata,
     output             wfull,
     output             rempty

src/vlog/rptr_empty.v

@@ -33,7 +33,8 @@ module rptr_empty
 
     reg  [ADDRSIZE:0] rbin;
     wire [ADDRSIZE:0] rgraynext, rbinnext;
-    
+    wire rempty_val;
+
     //-------------------
     // GRAYSTYLE2 pointer
     //-------------------

src/vlog/sync_r2w.v

@@ -23,7 +23,7 @@ module sync_r2w
     parameter ADDRSIZE = 4
     )(
     input  wire             wclk,
-    input  wire             wrst_ni,
+    input  wire             wrst_n,
     input      [ADDRSIZE:0] rptr,
     output reg [ADDRSIZE:0] wq2_rptr
     );

src/vlog/wptr_full.v

@@ -23,7 +23,9 @@ module wptr_full
     #(
     parameter ADDRSIZE = 4
     )(
-    input winc, wclk, wrst_n);
+    input winc,
+    input wclk,
+    input  wrst_n,
     input      [ADDRSIZE  :0] wq2_rptr,
     output reg                wfull,
     output     [ADDRSIZE-1:0] waddr,
@@ -32,7 +34,8 @@ module wptr_full
 
     reg  [ADDRSIZE:0] wbin;
     wire [ADDRSIZE:0] wgraynext, wbinnext;
-    
+    wire wfull_val;
+
     // GRAYSTYLE2 pointer
     always @(posedge wclk or negedge wrst_n)
         if (!wrst_n)