Start to correct FIFO behavior

Author: damofthemoon

sim/test/async_fifo_unit_test.sv

@@ -1,6 +1,6 @@
-`timescale 1 ns / 1 ps
 `include "svut_h.sv"
 `include "../../src/vlog/async_fifo.v"
+`timescale 1 ns / 1 ps
 
 module async_fifo_unit_test;
 
@@ -10,45 +10,53 @@ module async_fifo_unit_test;
     parameter POINTER = 4;
 
     reg              wr_clk;
-    reg              awresetn;
-    reg              wren;
-    reg  [WIDTH-1:0] data_in;
+    reg              wr_arstn;
+    reg              wr_en;
+    reg  [WIDTH-1:0] wr_data;
     wire             wr_full;
     reg              rd_clk;
-    reg              arresetn;
-    reg              rden;
-    wire [WIDTH-1:0] data_out;
+    reg              rd_arstn;
+    reg              rd_en;
+    wire [WIDTH-1:0] rd_data;
     wire             rd_empty;
 
     async_fifo 
     #(
-    ,
-    POINTER
+    .WIDTH (WIDTH),
+    .POINTER (POINTER)
     )
     dut 
     (
     wr_clk,
-    awresetn,
-    wren,
-    data_in,
+    wr_arstn,
+    wr_en,
+    wr_data,
     wr_full,
     rd_clk,
-    arresetn,
-    rden,
-    data_out,
+    rd_arstn,
+    rd_en,
+    rd_data,
     rd_empty
     );
 
     // An example to create a clock
-    // initial aclk = 0;
-    // always #2 aclk <= ~aclk;
+    initial wr_clk = 0;
+    initial rd_clk = 0;
+    always #2 wr_clk = ~wr_clk;
+    always #2 rd_clk = ~rd_clk;
 
     // An example to dump data for visualization
-    // initial $dumpvars(0,async_fifo_unit_test);
+    initial $dumpvars(0,async_fifo_unit_test);
 
     task setup();
     begin
-        // setup() runs when a test begins
+        wr_arstn = 1;
+        rd_arstn = 1;
+        init_write();
+        init_read();
+        #50;
+        wr_arstn = 1;
+        rd_arstn = 1;
     end
     endtask
 
@@ -58,10 +66,26 @@ module async_fifo_unit_test;
     end
     endtask
 
+    task init_write();
+    begin
+        wr_arstn = 0;
+        wr_en = 1'b0;
+        wr_data = 0;
+    end
+    endtask
+
+    task init_read();
+    begin
+        rd_arstn = 0;
+        rd_en = 1'b0;
+    end
+    endtask
+
     `UNIT_TESTS
 
-    `UNIT_TEST(TESTNAME)
-        // Describe here your testcase
+    `UNIT_TEST(INIT_FIFO)
+        wait (wr_full == 1'b0);
+        wait (rd_empty == 1'b0);
     `UNIT_TEST_END
 
     `UNIT_TESTS_END

src/vlog/async_fifo.v

@@ -25,38 +25,52 @@ module async_fifo
     )(
     // Write side of the FIFO
     input  wire             wr_clk,
-    input  wire             awresetn,
-    input  wire             wren,
-    input  wire [WIDTH-1:0] data_in,
+    input  wire             wr_arstn,
+    input  wire             wr_en,
+    input  wire [WIDTH-1:0] wr_data,
     output wire             wr_full,
     // Read side of the FIFO
     input  wire             rd_clk,
-    input  wire             arresetn,
-    input  wire             rden,
-    output wire [WIDTH-1:0] data_out,
+    input  wire             rd_arstn,
+    input  wire             rd_en,
+    output wire [WIDTH-1:0] rd_data,
     output wire             rd_empty
     );
 
     localparam DEPTH = 1 << POINTER;
 
-    reg  [POINTER-1 : 0] rd_pointer, rd_sync_1, rd_sync_2;
-    reg  [POINTER-1 : 0] wr_pointer, wr_sync_1, wr_sync_2;
-    wire [POINTER-1 : 0] rd_pointer_g;
-    wire [POINTER-1 : 0] wr_pointer_g;
+    // Read pointer managed by rd_clk
+    reg  [POINTER:0] rd_pointer;
+    // Write pointer managed by wr_clk
+    reg  [POINTER:0] wr_pointer;
 
-    reg [WIDTH-1 : 0] mem [DEPTH-1 : 0];
+    // Pointers used to pass between the domains
+    reg  [POINTER:0] rd_sync_1;
+    reg  [POINTER:0] wr_sync_1;
+    reg  [POINTER:0] rd_sync_2;
+    reg  [POINTER:0] wr_sync_2;
+    wire [POINTER:0] rd_pointer_g;
+    wire [POINTER:0] wr_pointer_g;
 
-    wire [POINTER-1 : 0] rd_pointer_sync;
-    wire [POINTER-1 : 0] wr_pointer_sync;
+    // Pointers used across the domains:
+
+    // Used in write domain
+    wire [POINTER:0] rd_pointer_sync;
+    // Used in read domain
+    wire [POINTER:0] wr_pointer_sync;
+
+    // The memory block RAM used to store and
+    // pass the information
+    reg  [WIDTH-1:0] mem [DEPTH-1 : 0];
 
     // Write logic management
-    always @(posedge wr_clk or posedge awresetn) begin
-        if (awresetn == 1'b0) begin
+    always @(posedge wr_clk or negedge wr_arstn) begin
+        if (wr_arstn == 1'b0) begin
             wr_pointer <= 0;
         end
-        else if (wr_full == 1'b0 && wren == 1'b1) begin
+        else if (wr_full == 1'b0 && wr_en == 1'b1) begin
             wr_pointer <= wr_pointer + 1;
-            mem[wr_pointer[POINTER-1 : 0]] <= data_in;
+            mem[wr_pointer[POINTER-1 : 0]] <= wr_data;
         end
     end
 
@@ -67,16 +81,16 @@ module async_fifo
     end
 
     // Read logic management
-    always @(posedge rd_clk or posedge arresetn) begin
-        if (arresetn == 1'b0) begin
+    always @(posedge rd_clk or negedge rd_arstn) begin
+        if (rd_arstn == 1'b0) begin
             rd_pointer <= 0;
         end
-        else if (rd_empty == 1'b0 && rden == 1'b1) begin
+        else if (rd_empty == 1'b0 && rd_en == 1'b1) begin
             rd_pointer <= rd_pointer + 1;
         end
     end
 
-    assign data_out = mem[rd_pointer[POINTER-1 : 0]];
+    assign rd_data = mem[rd_pointer[POINTER-1 : 0]];
 
     // Write pointer synchronization with read clock
     always @(posedge rd_clk) begin
@@ -85,13 +99,13 @@ module async_fifo
     end
 
     // Binary pointer comparaison
-    assign wr_full = ((wr_pointer[POINTER-1 : 0] == rd_pointer_sync[POINTER-1 : 0]) &&
-                    (wr_pointer[POINTER] != rd_pointer_sync[POINTER] ));
+    //assign wr_full = ((wr_pointer[POINTER-1 : 0] == rd_pointer_sync[POINTER-1 : 0]) &&
+    //                  (wr_pointer[POINTER] != rd_pointer_sync[POINTER] )) ? 1'b1 : 1'b0;
 
     // Gray counter comparaison
-    //assign wr_full  = ((wr_pointer[POINTER-2 : 0] == rd_pointer_sync[POINTER-2 : 0]) &&
-    //                (wr_pointer[POINTER-1] != rd_pointer_sync[POINTER-1]) &&
-    //                (wr_pointer[POINTER] != rd_pointer_sync[POINTER]));
+    assign wr_full  = ((wr_pointer[POINTER-2 : 0] == rd_pointer_sync[POINTER-2 : 0]) &&
+                       (wr_pointer[POINTER-1] != rd_pointer_sync[POINTER-1]) &&
+                       (wr_pointer[POINTER] != rd_pointer_sync[POINTER])) ? 1'b1 : 1'b0;
 
     // The FIFO is considered as empty when pointer match the same address
     // No more data remains to read
@@ -106,11 +120,9 @@ module async_fifo
 
     // Convert back to binary after the synchronization from
     // the source domain
-    assign wr_pointer_sync = wr_sync_2 ^ (wr_sync_2 >> 1) ^
-                            (wr_sync_2 >> 2) ^ (wr_sync_2 >> 3);
+    assign wr_pointer_sync = wr_sync_2 ^ (wr_sync_2 >> 1) ^ (wr_sync_2 >> 2) ^ (wr_sync_2 >> 3);
 
-    assign rd_pointer_sync = rd_sync_2 ^ (rd_sync_2 >> 1) ^
-                            (rd_sync_2 >> 2) ^ (rd_sync_2 >> 3);
+    assign rd_pointer_sync = rd_sync_2 ^ (rd_sync_2 >> 1) ^ (rd_sync_2 >> 2) ^ (rd_sync_2 >> 3);
 
 endmodule