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npu:phytium Add the driver for Phytium NPU engine
This patch adds the NPU driver, which will driver the neural network processing unit. You can use this driver to do picture classification and intelligent recognition, it will be a good AI module. Signed-off-by: yuanxia <[email protected]> Signed-off-by: Cheng Quan <[email protected]> Signed-off-by: Wang Yinfeng <[email protected]>
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‎drivers/staging/Kconfig

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@@ -80,4 +80,5 @@ source "drivers/staging/qlge/Kconfig"
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source "drivers/staging/vme_user/Kconfig"
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source "drivers/staging/phytium-npu/Kconfig"
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endif # STAGING

‎drivers/staging/Makefile

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@@ -29,3 +29,4 @@ obj-$(CONFIG_PI433) += pi433/
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obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/
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obj-$(CONFIG_FIELDBUS_DEV) += fieldbus/
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obj-$(CONFIG_QLGE) += qlge/
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obj-$(CONFIG_PHYTIUM_NPU) += phytium-npu/

‎drivers/staging/phytium-npu/Kconfig

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# SPDX-License-Identifier: GPL-2.0
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menuconfig PHYTIUM_NPU
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tristate "Phytium neural network processing unit"
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depends on ARCH_PHYTIUM
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help
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Say Y here if your want support for Phytium NPU controller framework.
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This is common support for devices that embed the Phytium NPU IP.
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To compile this driver as a module, choose M here: the module will be
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called phytium_npu.
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if PHYTIUM_NPU
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choice
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prompt "Select the Phytium NPU Hardware"
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default y
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help
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You need to select a suitable NPU controller in the current board.
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This option allows you to decide which Phytium NPU will be built
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in system.
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If in doubt, select 'N'
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config NPU_PLATFORM
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tristate "driver runs on platform"
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help
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Say Y here if you want to support for IO Mapped Phytium NPU controller.
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This support is for devices that have the Phytium NPU controller IP.
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To compile this driver as a module, choose M here: the module will be
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called phytium_npu_platform.
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config NPU_PCI
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tristate "driver runs on PCI hardware"
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help
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Say Y here if you want to support for Phytium NPU controller connected
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to the PCI bus. This support is for devices that have the Phytium NPU
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controller IP embedded into a PCI device.
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To compile this driver as a module, choose M here: the module will be
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called phytium_npu_pci.
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endchoice
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endif

‎drivers/staging/phytium-npu/Makefile

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# SPDX-License-Identifier: GPL-2.0
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ccflags-y += -I$(src)/include/
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ifdef CONFIG_NPU_PLATFORM
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ifeq ($(CONFIG_NPU_PLATFORM),m)
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EXTRA_CFLAGS += -DPHYTIUM_NPU_PLATFORM
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endif
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ifeq ($(CONFIG_NPU_PLATFORM),y)
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EXTRA_CFLAGS += -DPHYTIUM_NPU_PLATFORM
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endif
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endif
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obj-$(CONFIG_PHYTIUM_NPU) += phytium_npu.o
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phytium_npu-y := phytium_npu_common.o phytium_npu_dev.o \
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phytium_npu_dev_mmu.o phytium_npu_mm_mmu.o phytium_npu_workqueue.o \
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phytium_npu_session.o phytium_npu_uapi.o phytium_npu_debug.o
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obj-$(CONFIG_NPU_PLATFORM) += phytium_npu_platform.o
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obj-$(CONFIG_NPU_PCI) += phytium_npu_pci.o

‎drivers/staging/phytium-npu/Makefile.testing

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# SPDX-License-Identifier: GPL-2.0
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export CONFIG_PHYTIUM_NPU := y
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export CONFIG_NPU_PLATFORM := y
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export CONFIG_PHYTIUM_NPU_DMA_HEAP := y
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include Makefile
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ARCH := arm64
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CROSS_COMPILE := aarch64-linux-gnu-
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#------------------------------------
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# for internal use
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#------------------------------------
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ifeq ($(KERNELRELEASE),)
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#KDIR ?= /lib/modules/$(shell uname -r)/build
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KSRC := /home/chengquan/code/phytium-linux-kernel-master/
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PWD := $(shell pwd)
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# kernel warning levels: as high as possible:
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# W=12 and W=123 seem to warn about linux kernel headers, so use W=1.
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KWARN := W=1
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ifneq (,$(shell which sparse))
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# C=1: use 'sparse' for extra warnings, if it is avail.
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SPARSE := C=1
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endif
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all: modules
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modules:
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$(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE)-C $(KSRC) M=$(shell pwd) modules
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clean:
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$(MAKE) -C $(KDIR) M=$(PWD) clean
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check:
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cd $(KDIR); scripts/checkpatch.pl -f `find $(PWD)/include -name "*\.[ch]"`
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endif # KERNELRELEASE

‎drivers/staging/phytium-npu/include/phytium_npu.h

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/* SPDX-License-Identifier: GPL */
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/*
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* Copyright (C) 2023 Phytium Technology Co., Ltd.
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*/
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#ifndef __PHYTIUM_NPU_H__
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#define __PHYTIUM_NPU_H__
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/miscdevice.h>
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#include <linux/iosys-map.h>
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#include "phytium_npu_mmu.h"
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#define NPU_SUPPORT_SESSION_NUM 128
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#ifndef TRUE
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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#define NPU_STREAM_NONE 0x0
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#define NPU_STREAM_IN_HW 0x1
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#define NPU_STREAM_SCHEDULED 0x09
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#define NPU_STREAM_BUFF_IN_HW 0x10
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#define NPU_STREAM_BUFF_NO_READY 0x11
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#define NPU_STREAM_BUFF_BUSY 0x12
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#define NPU_STREAM_INFER_NONE 0x0
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#define NPU_STREAM_INFER_WAIT 0x2
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#define NPU_STREAM_INFER_WORK 0x3
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#define NPU_STREAM_INFER_DONE 0x4
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#define NPU_MMU_CONTEXT_NUM 2
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#define NPU_MMU_CONTEXT_MODULE_ID 0
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#define NPU_MMU_CONTEXT_IO_ID 1
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#define NEED_NOTHING 0x0
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#define NEED_SCHEDULE 0x1
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#define NEED_QUEUE_STREAM 0x2
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#define NPU_AUTO_SUSPEND_TIMEOUT 5000
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#define NPU_ACPI_POWER_TYPE 0x1
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#define GET_TIME_NS(ts) ktime_get_real_ts64(ts)
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/* state of the NPU device: power up or down */
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enum npu_power_state {
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NPU_STATE_OFF,
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NPU_STATE_ON
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};
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struct phytium_npu_stream;
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struct phytium_npu_debugfs {
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u32 debug_mode; /* register|mem file */
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/* perf|band|crc|PB_stream|PB_layer|PB_pass|crc_stream|crc_layer|crc|pass */
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u32 debug_type;
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u32 debug_fd; /* debug perf or band memory fd */
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u32 debug_crc_fd; /* debug crc memory fd */
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u32 debug_size;
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u64 debug_addr;
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u64 debug_crc_addr;
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struct iosys_map debug_map;
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struct iosys_map debug_crc_map;
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struct dentry *sess_dbgfs_dir;
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};
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struct phytium_npu_session {
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struct phytium_npu_dev *npu_dev;
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struct list_head sess_list_entry;
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struct list_head sched_list_entry;
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struct list_head stream_list;
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struct list_head response_list;
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struct list_head map_mmu_list;
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struct phytium_npu_mmu_context mmu_ctx[NPU_MMU_CONTEXT_NUM];
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struct npu_mmu_ctx *share_mctx; //mctx is belong to sesson
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struct phytium_npu_debugfs dbgfs;
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wait_queue_head_t response_wq;
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int id;
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};
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struct phytium_npu_dev {
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struct platform_device *pdev;
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struct device *dev;
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struct miscdevice miscdev;
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struct list_head sessions_list;
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struct list_head sched_sess_list;
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struct dentry *dbgfs_root_dir;
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struct phytium_npu_stream *activated_stream; /* stream had work on hardware */
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struct phytium_npu_stream *queued_stream; /* stream wait for activate */
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struct workqueue_struct *stream_wq;
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struct work_struct stream_work;
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struct delayed_work rt_delay_work;
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struct npu_mmu_config_global nmmu_config;
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struct mutex mutex_lock; /* protect stream */
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spinlock_t spin_irq_lock; /* protect interrupt */
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int used_mmu_context_id[4];
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u32 irq_status;
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int sessions_count;
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int is_cache_stream_on;
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int is_use_repeat;
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int is_platform_dev;
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int irq;
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int power_status;
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int load_status;
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int voltage_val;
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int clock_freq;
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void __iomem *reg_base;
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void __iomem *power_reg_base;
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struct timespec64 ts;
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struct timespec64 te;
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struct timespec64 tspan;
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};
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struct npu_user_stream_rsp {
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struct phytium_npu_session *session;
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struct list_head stream_rsp_list_entry;
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int rsp_size;
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struct npu_user_rsp ursp;
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};
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struct phytium_npu_stream {
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struct phytium_npu_session *session;
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struct list_head stream_list_entry;
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struct npu_user_stream_rsp *rsp;
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int stream_status; /* NONE|IN HARDWARE */
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int infer_status; /* NONE|QUEUED|WORK|DONE */
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int user_repeat_count; /* REPEAT COUNT */
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int all_buf_ready; /* NONE|READY */
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int is_rollback; /* NONE|ROLLBACK */
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struct npu_user_submit_stream nustream;
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};
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//extern shared function
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int phytium_npu_session_init(struct phytium_npu_dev *npu, struct phytium_npu_session *session);
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struct phytium_npu_session *phytium_npu_session_create(struct device *dev);
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int phytium_npu_register_dev(struct device *dev, void *plat_data, void __iomem *reg_base);
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int phytium_npu_register_misc(struct phytium_npu_dev *npudev);
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int phytium_npu_unregister_misc(struct phytium_npu_dev *npudev);
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int phytium_npu_session_release(struct phytium_npu_dev *npu, struct phytium_npu_session *session);
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struct npu_mctx_map *phytium_npu_find_mmu_ctx_map(struct phytium_npu_session *sess, int dma_buf_fd);
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struct dma_buf *phytium_npu_check_and_get_dma_buf(struct phytium_npu_session *sess, int dma_buf_fd);
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struct phytium_npu_dev *phytium_npu_get_npudev(void);
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int phytium_npu_mmu_dev_init(struct phytium_npu_dev *npudev, int page_size);
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int phytium_npu_create_new_mmu_context(struct phytium_npu_dev *npu,
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struct phytium_npu_session *session);
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int phytium_npu_mmu_map_init(struct phytium_npu_dev *npu, struct phytium_npu_session *sess,
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struct npu_memory_map *usr_mmap);
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int phytium_npu_import_dmabuf(struct phytium_npu_dev *npu, struct phytium_npu_session *sess,
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struct npu_memory_map *usr_mmap);
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int phytium_npu_release_mmu_context(struct phytium_npu_dev *npu,
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struct phytium_npu_session *session);
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int phytium_npu_mmu_unmap(struct phytium_npu_dev *npu, struct phytium_npu_session *sess,
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struct npu_memory_unmap *usr_unmmap);
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void phytium_npu_mmu_output_status(struct phytium_npu_dev *npudev);
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int phytium_npu_mmu_config_dev_mmu(struct phytium_npu_session *sess);
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int phytium_npu_mmu_dev_flush_tlb(struct phytium_npu_dev *npudev, int ctxid);
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int phytium_npu_write_stream(struct phytium_npu_dev *npu, struct phytium_npu_session *sess,
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const char *stream_buf, size_t size);
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int phytium_npu_delete_stream(struct phytium_npu_dev *npu, struct phytium_npu_session *sess,
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struct npu_delete_stream *stream);
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int phytium_npu_handle_irq(struct device *dev);
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u32 phytium_npu_get_irq_status(struct phytium_npu_dev *npudev);
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u32 phytium_npu_get_irq_enable_status(struct phytium_npu_dev *npudev);
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void phytium_npu_clear_msi_irq(struct phytium_npu_dev *npudev);
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void phytium_npu_clear_irq_status(struct phytium_npu_dev *npudev, u32 event);
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void phytium_npu_config_preload(struct phytium_npu_dev *npudev);
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void phytium_npu_config_start_inference(struct phytium_npu_dev *npudev,
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struct phytium_npu_session *sess,
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struct phytium_npu_stream *nstream);
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int phytium_npu_handle_thread_irq(struct device *dev);
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int phytium_npu_hw_reset_self(struct phytium_npu_dev *npudev);
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void phytium_npu_config_hl_wdt(struct phytium_npu_dev *npudev);
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void phytium_npu_config_event(struct phytium_npu_dev *npudev, u32 events, int is_enable);
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u32 phytium_npu_get_axi_err_status(struct phytium_npu_dev *npudev);
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void phytium_npu_output_mem_wdt_err(struct phytium_npu_dev *npudev);
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void do_work(struct work_struct *work);
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void phytium_npu_schedule_stream_queues(struct phytium_npu_dev *npu, bool asynchronous);
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int phytium_npu_check_stream_buf_is_ready(struct phytium_npu_stream *nstream);
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void phytium_npu_set_stream_buf_status_with_fd(struct phytium_npu_session *sess,
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int fd, int status);
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void phytium_npu_repeat_stream(struct phytium_npu_session *sess, int stream_id, int is_repeat);
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void phytium_npu_change_schedule_session(struct phytium_npu_session *sess,
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struct phytium_npu_dev *npu,
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int is_change);
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int phytium_npu_config_dma_address(struct phytium_npu_session *sess,
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struct phytium_npu_stream *nstream);
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void phytium_npu_config_clock(struct phytium_npu_dev *sess, int is_enable);
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int phytium_npu_submit_stream(struct phytium_npu_dev *npu, struct phytium_npu_session *sess,
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struct phytium_npu_stream *nstream);
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int phytium_npu_prepare_hw_4_queued_stream(struct phytium_npu_dev *npu,
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struct phytium_npu_session *sess,
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struct phytium_npu_stream *nstream);
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int phytium_npu_try_excute_queued_stream(struct phytium_npu_dev *npu);
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int phytium_npu_rollback_stream(struct phytium_npu_dev *npu);
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int phytium_npu_update_activated_stream_4_err_mmu(struct phytium_npu_dev *npu);
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int phytium_npu_session_release_all(struct phytium_npu_dev *npudev);
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int phytium_npu_unregister_dev(struct device *dev);
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int phytiun_npu_check_debug_fs_cfg(struct phytium_npu_session *sess);
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void phytium_npu_debug_set_hw_register(struct phytium_npu_dev *npu,
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struct phytium_npu_session *sess);
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void phytium_npu_debugfs_init(struct phytium_npu_dev *npu);
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void phytium_npu_debugfs_session_init(struct phytium_npu_dev *npu,
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struct phytium_npu_session *sess);
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void phytium_npu_debug_show_register(struct phytium_npu_dev *npu, struct phytium_npu_session *sess);
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void phytium_npu_debugfs_session_remove(struct phytium_npu_session *sess);
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void phytium_npu_debugfs_remove(struct phytium_npu_dev *npu);
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void phytium_npu_try_resume_work(struct phytium_npu_dev *npudev);
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int phytium_npu_schedule_suspend(struct phytium_npu_dev *npudev, u32 delay_ms);
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int phytium_npu_common_resume(struct device *dev);
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int phytium_npu_common_suspend(struct device *dev);
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void phytium_npu_get_time_span(struct timespec64 *start, struct timespec64 *end,
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struct timespec64 *span);
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#endif

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