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base repository: qemu/qemu
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head repository: ekoeppen/qemu
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- 10 commits
- 17 files changed
- 2 contributors
Commits on Feb 10, 2013
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target-arm: Clear thumb state bit when popping PC during ARMV7M inter…
…rupt exit An operating system (e.g. FreeRTOS) may create a task by setting up a stack with a "simulated" stack frame containing the start address of the task. The OS will then start the task by switching to the stack and doing an interrupt return from within the service handler. If the start address is a function pointer, its thumb state bit (bit 0) will contain a 1 to indicate the first instruction is a thumb instruction (and in the ARMV7M architecture, all instructions are thumb instructions). When the interrupt returns, QEMU will pop the start address into the PC register. QEMU expects the PC register to be half-word aligned (which is enforced when branching), and will not run properly when the PC is odd. This patch clears bit 0 when restoring the PC during the ARMV7M interrupt exit. Note that there is a bug open against QEMU for this problem: https://bugs.launchpad.net/qemu/+bug/657006
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hw/armv7m_nvic: Implement byte read/write for ARMV7M SCB_SHPRx registers
Adds nvic_writeb and nvic_readb functions. Implements byte read/write for the ARMV7M SCB_SHPRx (System Handler Priority Registers). Currently, only double word access is implemented. The ARM CMSIS library maps these registers to a byte array, which requires that byte access be implemented. Note that because the NVIC ID register read handles both byte and word reads, it is left as-is, and not moved into the new nvic_readb function. Conflicts: hw/armv7m_nvic.c
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hw/armv7m_nvic: Add global variable for SysTick external reference clock
Adds a new external reference clock scale variable to complement the existing system_clock_scale variable. Previously, the value was hardcoded to 1000 when calculating the SysTick scale. The new variable defaults to 1000 to maintain backward compatibility.
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