testing branch changes

Author: ericxu233

DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/anr.hpp

@@ -7,7 +7,7 @@
 // ANR pipeline.
 //
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <limits>

DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/anr_params.hpp

@@ -1,7 +1,7 @@
 #ifndef __ANR_PARAMS_HPP__
 #define __ANR_PARAMS_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <sycl/ext/intel/ac_types/ac_fixed.hpp>
 #include <iostream>

DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/column_stencil.hpp

@@ -1,7 +1,7 @@
 #ifndef __COLUMN_STENCIL_HPP__
 #define __COLUMN_STENCIL_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "data_bundle.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/dma_kernels.hpp

@@ -7,7 +7,7 @@
 // the ANR output pipe and writing to device memory.
 //
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "data_bundle.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/intensity_sigma_lut.hpp

@@ -1,7 +1,7 @@
 #ifndef __INTENSITY_SIGMA_LUT_HPP__
 #define __INTENSITY_SIGMA_LUT_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <type_traits>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/main.cpp

@@ -1,4 +1,4 @@
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <algorithm>
 #include <array>

DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/row_stencil.hpp

@@ -1,7 +1,7 @@
 #ifndef __ROW_STENCIL_HPP__
 #define __ROW_STENCIL_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <limits>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/board_test.cpp

@@ -1,4 +1,4 @@
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <iostream>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/board_test.hpp

@@ -1,4 +1,4 @@
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <vector>
 
 #include "host_speed.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/helper.hpp

@@ -1,5 +1,5 @@
 // Header file to accompany board_test
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 
 constexpr size_t kKB = 1024;
 constexpr size_t kMB = 1024 * 1024;

DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/host_speed.hpp

@@ -1,5 +1,5 @@
 // Header file to accompany hostspeed tests
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <iomanip>
 #include <iostream>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp

@@ -1,7 +1,7 @@
 #ifndef __CHOLESKY_HPP__
 #define __CHOLESKY_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/ac_types/ac_complex.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>

DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/cholesky_demo.cpp

@@ -1,6 +1,6 @@
 #include <math.h>
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <list>
 #include <sycl/ext/intel/ac_types/ac_complex.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>

DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion.hpp

@@ -1,7 +1,7 @@
 #ifndef __CHOLESKY_INVERSION_HPP__
 #define __CHOLESKY_INVERSION_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/ac_types/ac_complex.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>

DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion_demo.cpp

@@ -1,6 +1,6 @@
 #include <math.h>
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <list>
 #include <sycl/ext/intel/ac_types/ac_complex.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>

DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/main.cpp

@@ -90,7 +90,7 @@
 //
 //
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <cstddef>
 #include <cstdlib>

DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/db.cpp

@@ -14,7 +14,7 @@
 #include <sys/stat.h>
 #include <sys/types.h>
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <algorithm>
 #include <chrono>

DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/query1/query1_kernel.hpp

@@ -2,7 +2,7 @@
 #define __QUERY1_KERNEL_HPP__
 #pragma once
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "../dbdata.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/query11/pipe_types.hpp

@@ -2,7 +2,7 @@
 #define __PIPE_TYPES_H__
 #pragma once
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "../db_utils/StreamingData.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/query11/query11_kernel.hpp

@@ -2,7 +2,7 @@
 #define __QUERY11_KERNEL_HPP__
 #pragma once
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "../dbdata.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/query12/pipe_types.hpp

@@ -2,7 +2,7 @@
 #define __PIPE_TYPES_H__
 #pragma once
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "../db_utils/StreamingData.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/query12/query12_kernel.hpp

@@ -2,7 +2,7 @@
 #define __QUERY12_KERNEL_HPP__
 #pragma once
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "../dbdata.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/query9/pipe_types.hpp

@@ -2,7 +2,7 @@
 #define __PIPE_TYPES_H__
 #pragma once
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "../db_utils/StreamingData.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/query9/query9_kernel.hpp

@@ -2,7 +2,7 @@
 #define __QUERY9_KERNEL_HPP__
 #pragma once
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "../dbdata.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/common/byte_stacker.hpp

@@ -1,7 +1,7 @@
 #ifndef __BYTE_STACKER_HPP__
 #define __BYTE_STACKER_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/common/common.hpp

@@ -1,7 +1,7 @@
 #ifndef __COMMON_HPP__
 #define __COMMON_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <functional>
 #include <iostream>
 #include <optional>

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/common/lz77_decoder.hpp

@@ -1,7 +1,7 @@
 #ifndef __LZ77_DECODER_HPP__
 #define __LZ77_DECODER_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/gzip/byte_bit_stream.hpp

@@ -1,7 +1,7 @@
 #ifndef __BYTE_BIT_STREAM_HPP__
 #define __BYTE_BIT_STREAM_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/gzip/gzip_decompressor.hpp

@@ -1,7 +1,7 @@
 #ifndef __GZIP_DECOMPRESSOR_HPP__
 #define __GZIP_DECOMPRESSOR_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <chrono>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/gzip/gzip_metadata_reader.hpp

@@ -1,7 +1,7 @@
 #ifndef __GZIP_METADATA_READER_HPP__
 #define __GZIP_METADATA_READER_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/gzip/huffman_decoder.hpp

@@ -1,7 +1,7 @@
 #ifndef __HUFFMAN_DECODER_HPP__
 #define __HUFFMAN_DECODER_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp

@@ -1,4 +1,4 @@
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <algorithm>
 #include <array>
 #include <fstream>

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/snappy/byte_stream.hpp

@@ -1,7 +1,7 @@
 #ifndef __BYTE_STREAM_HPP__
 #define __BYTE_STREAM_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/snappy/snappy_decompressor.hpp

@@ -1,7 +1,7 @@
 #ifndef __SNAPPY_DECOMPRESSOR_HPP__
 #define __SNAPPY_DECOMPRESSOR_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <chrono>
 #include <optional>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/snappy/snappy_reader.hpp

@@ -1,7 +1,7 @@
 #ifndef __SNAPPY_READER_HPP__
 #define __SNAPPY_READER_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/ac_types/ac_int.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/WriteGzip.cpp

@@ -9,7 +9,7 @@
 #include <sys/stat.h>
 #include <sys/types.h>
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <chrono>
 #include <string>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip.cpp

@@ -1,4 +1,4 @@
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <chrono>
 #include <fstream>

DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzip_ll.cpp

@@ -1,4 +1,4 @@
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <chrono>
 #include <fstream>

DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzipkernel.cpp

@@ -1,4 +1,4 @@
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 
 #include "gzipkernel.hpp"
 #include "kernels.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzipkernel.hpp

@@ -2,7 +2,7 @@
 #define __GZIPKERNEL_H__
 #pragma once
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 
 using namespace sycl;
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzipkernel_ll.cpp

@@ -41,7 +41,7 @@
   communicate that these pointers don't alias.
 */
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 #include <vector>
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/gzipkernel_ll.hpp

@@ -2,7 +2,7 @@
 #define __GZIPKERNEL_H__
 #pragma once
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include "kernels.hpp"
 
 using namespace sycl;

DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/consume.hpp

@@ -1,7 +1,7 @@
 #ifndef __CONSUME_HPP__
 #define __CONSUME_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 using namespace sycl;

DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/main.cpp

@@ -7,7 +7,7 @@
 #include <utility>
 #include <vector>
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 // dpc_common.hpp can be found in the dev-utilities include folder.

DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/merge.hpp

@@ -1,7 +1,7 @@
 #ifndef __MERGE_HPP__
 #define __MERGE_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "sorting_networks.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/merge_sort.hpp

@@ -7,7 +7,7 @@
 #include <type_traits>
 #include <vector>
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 #include "consume.hpp"

DirectProgramming/DPC++FPGA/ReferenceDesigns/merge_sort/src/produce.hpp

@@ -1,7 +1,7 @@
 #ifndef __PRODUCE_HPP__
 #define __PRODUCE_HPP__
 
-#include <sycl/sycl.hpp>
+#include <CL/sycl.hpp>
 #include <sycl/ext/intel/fpga_extensions.hpp>
 
 using namespace sycl;