@@ -51,6 +51,7 @@ LoRaClass::LoRaClass() :
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_ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN),
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_frequency(0 ),
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_packetIndex(0 ),
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+ _implicitHeaderMode(0 ),
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_onReceive(NULL )
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{
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}
@@ -110,11 +111,17 @@ void LoRaClass::end()
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SPI.end ();
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}
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- int LoRaClass::beginPacket ()
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+ int LoRaClass::beginPacket (bool implicitHeader )
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{
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// put in standby mode
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idle ();
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+ if (implicitHeader) {
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+ implicitHeaderMode ();
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+ } else {
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+ explicitHeaderMode ();
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+ }
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+
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// reset FIFO address and paload length
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writeRegister (REG_FIFO_ADDR_PTR, 0 );
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writeRegister (REG_PAYLOAD_LENGTH, 0 );
@@ -136,11 +143,19 @@ int LoRaClass::endPacket()
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return 1 ;
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}
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- int LoRaClass::parsePacket ()
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+ int LoRaClass::parsePacket (int size )
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{
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int packetLength = 0 ;
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int irqFlags = readRegister (REG_IRQ_FLAGS);
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+ if (size > 0 ) {
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+ implicitHeaderMode ();
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+
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+ writeRegister (REG_PAYLOAD_LENGTH, size & 0xff );
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+ } else {
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+ explicitHeaderMode ();
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+ }
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+
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// clear IRQ's
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writeRegister (REG_IRQ_FLAGS, irqFlags);
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@@ -149,7 +164,11 @@ int LoRaClass::parsePacket()
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_packetIndex = 0 ;
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// read packet length
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- packetLength = readRegister (REG_RX_NB_BYTES);
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+ if (_implicitHeaderMode) {
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+ packetLength = readRegister (REG_PAYLOAD_LENGTH);
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+ } else {
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+ packetLength = readRegister (REG_RX_NB_BYTES);
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+ }
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// set FIFO address to current RX address
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writeRegister (REG_FIFO_ADDR_PTR, readRegister (REG_FIFO_RX_CURRENT_ADDR));
@@ -255,8 +274,16 @@ void LoRaClass::onReceive(void(*callback)(int))
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}
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}
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- void LoRaClass::receive ()
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+ void LoRaClass::receive (int size )
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{
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+ if (size > 0 ) {
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+ implicitHeaderMode ();
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+
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+ writeRegister (REG_PAYLOAD_LENGTH, size & 0xff );
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+ } else {
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+ explicitHeaderMode ();
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+ }
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+
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writeRegister (REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
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}
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@@ -299,15 +326,19 @@ void LoRaClass::setTxPower(int level)
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void LoRaClass::setSpreadingFactor (int sf)
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{
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- if (sf < 7 ) {
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- sf = 7 ;
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+ if (sf < 6 ) {
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+ sf = 6 ;
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} else if (sf > 12 ) {
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sf = 12 ;
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}
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- writeRegister (REG_MODEM_CONFIG_1, readRegister (REG_MODEM_CONFIG_1) & 0xfe );
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- writeRegister (REG_DETECTION_OPTIMIZE, 0xc3 );
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- writeRegister (REG_DETECTION_THRESHOLD, 0x0a );
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+ if (sf == 6 ) {
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+ writeRegister (REG_DETECTION_OPTIMIZE, 0xc5 );
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+ writeRegister (REG_DETECTION_THRESHOLD, 0x0c );
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+ } else {
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+ writeRegister (REG_DETECTION_OPTIMIZE, 0xc3 );
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+ writeRegister (REG_DETECTION_THRESHOLD, 0x0a );
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+ }
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writeRegister (REG_MODEM_CONFIG_2, (readRegister (REG_MODEM_CONFIG_2) & 0x0f ) | ((sf << 4 ) & 0xf0 ));
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}
@@ -392,6 +423,20 @@ void LoRaClass::dumpRegisters(Stream& out)
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}
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}
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+ void LoRaClass::explicitHeaderMode ()
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+ {
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+ _implicitHeaderMode = 0 ;
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+
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+ writeRegister (REG_MODEM_CONFIG_1, readRegister (REG_MODEM_CONFIG_1) & 0xfe );
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+ }
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+
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+ void LoRaClass::implicitHeaderMode ()
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+ {
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+ _implicitHeaderMode = 1 ;
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+
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+ writeRegister (REG_MODEM_CONFIG_1, readRegister (REG_MODEM_CONFIG_1) | 0x01 );
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+ }
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+
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void LoRaClass::handleDio0Rise ()
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{
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int irqFlags = readRegister (REG_IRQ_FLAGS);
@@ -404,7 +449,7 @@ void LoRaClass::handleDio0Rise()
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_packetIndex = 0 ;
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// read packet length
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- int packetLength = readRegister (REG_RX_NB_BYTES);
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+ int packetLength = _implicitHeaderMode ? readRegister (REG_PAYLOAD_LENGTH) : readRegister (REG_RX_NB_BYTES);
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// set FIFO address to current RX address
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writeRegister (REG_FIFO_ADDR_PTR, readRegister (REG_FIFO_RX_CURRENT_ADDR));
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