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torvaldstorvalds
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Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, tsc: Skip TSC synchronization checks for tsc=reliable clocksource: Convert tcb_clksrc to use clocksource_register_hz/khz clocksource: cris: Convert to clocksource_register_khz clocksource: xtensa: Convert to clocksource_register_hz/khz clocksource: um: Convert to clocksource_register_hz/khz clocksource: parisc: Convert to clocksource_register_hz/khz clocksource: m86k: Convert to clocksource_register_hz/khz time: x86: Replace LATCH with PIT_LATCH in i8253 clocksource driver time: x86: Remove CLOCK_TICK_RATE from acpi_pm clocksource driver time: x86: Remove CLOCK_TICK_RATE from mach_timer.h time: x86: Remove CLOCK_TICK_RATE from tsc code time: Fix spelling mistakes in new comments time: fix bogus comment in timekeeping_get_ns_raw
2 parents 0db49b7 + 0518469 commit 376613e

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17 files changed

+28
-58
lines changed

17 files changed

+28
-58
lines changed

‎arch/cris/arch-v32/kernel/time.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,14 +47,12 @@ static struct clocksource cont_rotime = {
4747
.rating = 300,
4848
.read = read_cont_rotime,
4949
.mask = CLOCKSOURCE_MASK(32),
50-
.shift = 10,
5150
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
5251
};
5352

5453
static int __init etrax_init_cont_rotime(void)
5554
{
56-
cont_rotime.mult = clocksource_khz2mult(100000, cont_rotime.shift);
57-
clocksource_register(&cont_rotime);
55+
clocksource_register_khz(&cont_rotime, 100000);
5856
return 0;
5957
}
6058
arch_initcall(etrax_init_cont_rotime);

‎arch/m68k/platform/68328/timers.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,6 @@ static struct clocksource m68328_clk = {
9393
.name = "timer",
9494
.rating = 250,
9595
.read = m68328_read_clk,
96-
.shift = 20,
9796
.mask = CLOCKSOURCE_MASK(32),
9897
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
9998
};
@@ -115,8 +114,7 @@ void hw_timer_init(void)
115114

116115
/* Enable timer 1 */
117116
TCTL |= TCTL_TEN;
118-
m68328_clk.mult = clocksource_hz2mult(TICKS_PER_JIFFY*HZ, m68328_clk.shift);
119-
clocksource_register(&m68328_clk);
117+
clocksource_register_hz(&m68328_clk, TICKS_PER_JIFFY*HZ);
120118
}
121119

122120
/***************************************************************************/

‎arch/m68k/platform/coldfire/dma_timer.c

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,6 @@ static struct clocksource clocksource_cf_dt = {
4444
.rating = 200,
4545
.read = cf_dt_get_cycles,
4646
.mask = CLOCKSOURCE_MASK(32),
47-
.shift = 20,
4847
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
4948
};
5049

@@ -60,9 +59,7 @@ static int __init init_cf_dt_clocksource(void)
6059
__raw_writeb(0x00, DTER0);
6160
__raw_writel(0x00000000, DTRR0);
6261
__raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
63-
clocksource_cf_dt.mult = clocksource_hz2mult(DMA_FREQ,
64-
clocksource_cf_dt.shift);
65-
return clocksource_register(&clocksource_cf_dt);
62+
return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
6663
}
6764

6865
arch_initcall(init_cf_dt_clocksource);

‎arch/m68k/platform/coldfire/pit.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,6 @@ static struct clocksource pit_clk = {
144144
.name = "pit",
145145
.rating = 100,
146146
.read = pit_read_clk,
147-
.shift = 20,
148147
.mask = CLOCKSOURCE_MASK(32),
149148
};
150149

@@ -162,8 +161,7 @@ void hw_timer_init(void)
162161

163162
setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
164163

165-
pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift);
166-
clocksource_register(&pit_clk);
164+
clocksource_register_hz(&pit_clk, FREQ);
167165
}
168166

169167
/***************************************************************************/

‎arch/m68k/platform/coldfire/sltimers.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,6 @@ static struct clocksource mcfslt_clk = {
114114
.name = "slt",
115115
.rating = 250,
116116
.read = mcfslt_read_clk,
117-
.shift = 20,
118117
.mask = CLOCKSOURCE_MASK(32),
119118
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
120119
};
@@ -136,8 +135,7 @@ void hw_timer_init(void)
136135

137136
setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
138137

139-
mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
140-
clocksource_register(&mcfslt_clk);
138+
clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
141139

142140
#ifdef CONFIG_HIGHPROFILE
143141
mcfslt_profile_init();

‎arch/m68k/platform/coldfire/timers.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,6 @@ static struct clocksource mcftmr_clk = {
8888
.name = "tmr",
8989
.rating = 250,
9090
.read = mcftmr_read_clk,
91-
.shift = 20,
9291
.mask = CLOCKSOURCE_MASK(32),
9392
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
9493
};
@@ -109,8 +108,7 @@ void hw_timer_init(void)
109108
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
110109
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
111110

112-
mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
113-
clocksource_register(&mcftmr_clk);
111+
clocksource_register_hz(&mcftmr_clk, FREQ);
114112

115113
setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
116114

‎arch/parisc/kernel/time.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -198,8 +198,6 @@ static struct clocksource clocksource_cr16 = {
198198
.rating = 300,
199199
.read = read_cr16,
200200
.mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
201-
.mult = 0, /* to be set */
202-
.shift = 22,
203201
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
204202
};
205203

@@ -270,7 +268,5 @@ void __init time_init(void)
270268

271269
/* register at clocksource framework */
272270
current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */
273-
clocksource_cr16.mult = clocksource_khz2mult(current_cr16_khz,
274-
clocksource_cr16.shift);
275-
clocksource_register(&clocksource_cr16);
271+
clocksource_register_khz(&clocksource_cr16, current_cr16_khz);
276272
}

‎arch/um/kernel/time.c

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -75,8 +75,6 @@ static struct clocksource itimer_clocksource = {
7575
.rating = 300,
7676
.read = itimer_read,
7777
.mask = CLOCKSOURCE_MASK(64),
78-
.mult = 1000,
79-
.shift = 0,
8078
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
8179
};
8280

@@ -94,9 +92,9 @@ static void __init setup_itimer(void)
9492
clockevent_delta2ns(60 * HZ, &itimer_clockevent);
9593
itimer_clockevent.min_delta_ns =
9694
clockevent_delta2ns(1, &itimer_clockevent);
97-
err = clocksource_register(&itimer_clocksource);
95+
err = clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC);
9896
if (err) {
99-
printk(KERN_ERR "clocksource_register returned %d\n", err);
97+
printk(KERN_ERR "clocksource_register_hz returned %d\n", err);
10098
return;
10199
}
102100
clockevents_register_device(&itimer_clockevent);

‎arch/x86/include/asm/mach_timer.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515

1616
#define CALIBRATE_TIME_MSEC 30 /* 30 msecs */
1717
#define CALIBRATE_LATCH \
18-
((CLOCK_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000)
18+
((PIT_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000)
1919

2020
static inline void mach_prepare_counter(void)
2121
{

‎arch/x86/include/asm/tsc.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,8 @@ extern int unsynchronized_tsc(void);
5151
extern int check_tsc_unstable(void);
5252
extern unsigned long native_calibrate_tsc(void);
5353

54+
extern int tsc_clocksource_reliable;
55+
5456
/*
5557
* Boot-time check whether the TSCs are synchronized across
5658
* all CPUs/cores:

‎arch/x86/kernel/tsc.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ static int __read_mostly tsc_unstable;
3535
erroneous rdtsc usage on !cpu_has_tsc processors */
3636
static int __read_mostly tsc_disabled = -1;
3737

38-
static int tsc_clocksource_reliable;
38+
int tsc_clocksource_reliable;
3939
/*
4040
* Scheduler clock - returns current time in nanosec units.
4141
*/
@@ -178,11 +178,11 @@ static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
178178
}
179179

180180
#define CAL_MS 10
181-
#define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
181+
#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
182182
#define CAL_PIT_LOOPS 1000
183183

184184
#define CAL2_MS 50
185-
#define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS))
185+
#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
186186
#define CAL2_PIT_LOOPS 5000
187187

188188

‎arch/x86/kernel/tsc_sync.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,7 @@ void __cpuinit check_tsc_sync_source(int cpu)
113113
if (unsynchronized_tsc())
114114
return;
115115

116-
if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
116+
if (tsc_clocksource_reliable) {
117117
if (cpu == (nr_cpu_ids-1) || system_state != SYSTEM_BOOTING)
118118
pr_info(
119119
"Skipped synchronization checks as TSC is reliable.\n");
@@ -172,7 +172,7 @@ void __cpuinit check_tsc_sync_target(void)
172172
{
173173
int cpus = 2;
174174

175-
if (unsynchronized_tsc() || boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
175+
if (unsynchronized_tsc() || tsc_clocksource_reliable)
176176
return;
177177

178178
/*

‎arch/xtensa/kernel/time.c

Lines changed: 1 addition & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -41,14 +41,6 @@ static struct clocksource ccount_clocksource = {
4141
.rating = 200,
4242
.read = ccount_read,
4343
.mask = CLOCKSOURCE_MASK(32),
44-
/*
45-
* With a shift of 22 the lower limit of the cpu clock is
46-
* 1MHz, where NSEC_PER_CCOUNT is 1000 or a bit less than
47-
* 2^10: Since we have 32 bits and the multiplicator can
48-
* already take up as much as 10 bits, this leaves us with
49-
* remaining upper 22 bits.
50-
*/
51-
.shift = 22,
5244
};
5345

5446
static irqreturn_t timer_interrupt(int irq, void *dev_id);
@@ -66,10 +58,7 @@ void __init time_init(void)
6658
printk("%d.%02d MHz\n", (int)ccount_per_jiffy/(1000000/HZ),
6759
(int)(ccount_per_jiffy/(10000/HZ))%100);
6860
#endif
69-
ccount_clocksource.mult =
70-
clocksource_hz2mult(CCOUNT_PER_JIFFY * HZ,
71-
ccount_clocksource.shift);
72-
clocksource_register(&ccount_clocksource);
61+
clocksource_register_hz(&ccount_clocksource, CCOUNT_PER_JIFFY * HZ);
7362

7463
/* Initialize the linux timer interrupt. */
7564

‎drivers/clocksource/acpi_pm.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
143143
#ifndef CONFIG_X86_64
144144
#include <asm/mach_timer.h>
145145
#define PMTMR_EXPECTED_RATE \
146-
((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10))
146+
((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (PIT_TICK_RATE>>10))
147147
/*
148148
* Some boards have the PMTMR running way too fast. We check
149149
* the PMTMR rate against PIT channel 2 to catch these cases.

‎drivers/clocksource/i8253.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ static cycle_t i8253_read(struct clocksource *cs)
5353
count |= inb_p(PIT_CH0) << 8;
5454

5555
/* VIA686a test code... reset the latch if count > max + 1 */
56-
if (count > LATCH) {
56+
if (count > PIT_LATCH) {
5757
outb_p(0x34, PIT_MODE);
5858
outb_p(PIT_LATCH & 0xff, PIT_CH0);
5959
outb_p(PIT_LATCH >> 8, PIT_CH0);
@@ -114,8 +114,8 @@ static void init_pit_timer(enum clock_event_mode mode,
114114
case CLOCK_EVT_MODE_PERIODIC:
115115
/* binary, mode 2, LSB/MSB, ch 0 */
116116
outb_p(0x34, PIT_MODE);
117-
outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
118-
outb_p(LATCH >> 8 , PIT_CH0); /* MSB */
117+
outb_p(PIT_LATCH & 0xff , PIT_CH0); /* LSB */
118+
outb_p(PIT_LATCH >> 8 , PIT_CH0); /* MSB */
119119
break;
120120

121121
case CLOCK_EVT_MODE_SHUTDOWN:

‎drivers/clocksource/tcb_clksrc.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,6 @@ static struct clocksource clksrc = {
5959
.rating = 200,
6060
.read = tc_get_cycles,
6161
.mask = CLOCKSOURCE_MASK(32),
62-
.shift = 18,
6362
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
6463
};
6564

@@ -256,7 +255,6 @@ static int __init tcb_clksrc_init(void)
256255
best_divisor_idx = i;
257256
}
258257

259-
clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
260258

261259
printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
262260
divided_rate / 1000000,
@@ -292,7 +290,7 @@ static int __init tcb_clksrc_init(void)
292290
__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
293291

294292
/* and away we go! */
295-
clocksource_register(&clksrc);
293+
clocksource_register_hz(&clksrc, divided_rate);
296294

297295
/* channel 2: periodic and oneshot timer support */
298296
setup_clkevents(tc, clk32k_divisor_idx);

‎kernel/time/timekeeping.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@ static inline s64 timekeeping_get_ns_raw(void)
131131
/* calculate the delta since the last update_wall_time: */
132132
cycle_delta = (cycle_now - clock->cycle_last) & clock->mask;
133133

134-
/* return delta convert to nanoseconds using ntp adjusted mult. */
134+
/* return delta convert to nanoseconds. */
135135
return clocksource_cyc2ns(cycle_delta, clock->mult, clock->shift);
136136
}
137137

@@ -813,11 +813,11 @@ static void timekeeping_adjust(s64 offset)
813813
* First we shift it down from NTP_SHIFT to clocksource->shifted nsecs.
814814
*
815815
* Note we subtract one in the shift, so that error is really error*2.
816-
* This "saves" dividing(shifting) intererval twice, but keeps the
817-
* (error > interval) comparision as still measuring if error is
816+
* This "saves" dividing(shifting) interval twice, but keeps the
817+
* (error > interval) comparison as still measuring if error is
818818
* larger then half an interval.
819819
*
820-
* Note: It does not "save" on aggrivation when reading the code.
820+
* Note: It does not "save" on aggravation when reading the code.
821821
*/
822822
error = timekeeper.ntp_error >> (timekeeper.ntp_error_shift - 1);
823823
if (error > interval) {
@@ -833,7 +833,7 @@ static void timekeeping_adjust(s64 offset)
833833
* nanosecond, and store the amount rounded up into
834834
* the error. This causes the likely below to be unlikely.
835835
*
836-
* The properfix is to avoid rounding up by using
836+
* The proper fix is to avoid rounding up by using
837837
* the high precision timekeeper.xtime_nsec instead of
838838
* xtime.tv_nsec everywhere. Fixing this will take some
839839
* time.

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