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Commit 4718e65

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dh73
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Tested and working altsyncarm without init files
1 parent e480847 commit 4718e65

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2 files changed

+59
-57
lines changed

2 files changed

+59
-57
lines changed

‎techlibs/intel/common/brams_map.v

Lines changed: 34 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -31,44 +31,42 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
3131
CFG_DBITS == 36 ? 9:
3232
'bx;
3333

34-
localparam NUMWORDS = CFG_DBITS == 1 ? "8192":
35-
CFG_DBITS == 2 ? "4096":
36-
CFG_DBITS == 4 ? "2048":
37-
CFG_DBITS == 8 ? "1024":
38-
CFG_DBITS == 9 ? "1024":
39-
CFG_DBITS == 16 ? "512":
40-
CFG_DBITS == 18 ? "512":
41-
CFG_DBITS == 32 ? "256":
42-
CFG_DBITS == 36 ? "256":
34+
localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
35+
CFG_DBITS == 2 ? 4096:
36+
CFG_DBITS == 4 ? 2048:
37+
CFG_DBITS == 8 ? 1024:
38+
CFG_DBITS == 9 ? 1024:
39+
CFG_DBITS == 16 ? 512:
40+
CFG_DBITS == 18 ? 512:
41+
CFG_DBITS == 32 ? 256:
42+
CFG_DBITS == 36 ? 256:
4343
'bx;
44-
/* Killing some stupid warnings and assignations*/
45-
/* generate
46-
if( MODE == 1 ) begin
47-
assign B1DATA_t = ({34{1'b0},B1DATA[0]});
48-
end
49-
endgenerate*/
5044

51-
altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
52-
.clock_enable_input_a ("ALTERNATE" ),
53-
.clock_enable_output_b ("NORMAL" ),
54-
.clock_enable_output_a ("NORMAL" ),
55-
.wrcontrol_aclr_a ("NONE" ),
56-
.indata_aclr_a ("NONE" ),
57-
.address_aclr_a ("NONE" ),
58-
.outdata_aclr_a ("NONE" ),
59-
.outdata_reg_a ("UNREGISTERED"),
60-
.operation_mode ("SINGLE_PORT" ),
61-
.intended_device_family ("CYCLONE IVE" ),
62-
.outdata_reg_a ("UNREGISTERED"),
63-
.lpm_type ("altsyncram" ),
64-
.init_type ("unused" ),
65-
.ram_block_type ("AUTO" ),
66-
.numwords_b ( NUMWORDS ),
67-
.numwords_a ( NUMWORDS ),
68-
.widthad_b ( CFG_ABITS ),
69-
.width_b ( CFG_DBITS ),
70-
.widthad_a ( CFG_ABITS ),
71-
.width_a ( CFG_DBITS )
45+
altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
46+
.clock_enable_input_a ("ALTERNATE" ),
47+
.clock_enable_output_b ("NORMAL" ),
48+
.clock_enable_output_a ("NORMAL" ),
49+
.wrcontrol_aclr_a ("NONE" ),
50+
.indata_aclr_a ("NONE" ),
51+
.address_aclr_a ("NONE" ),
52+
.outdata_aclr_a ("NONE" ),
53+
.outdata_reg_a ("UNREGISTERED"),
54+
.operation_mode ("SINGLE_PORT" ),
55+
.intended_device_family ("CYCLONE IVE" ),
56+
.outdata_reg_a ("UNREGISTERED"),
57+
.lpm_type ("altsyncram" ),
58+
.init_type ("unused" ),
59+
.ram_block_type ("AUTO" ),
60+
.lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
61+
.power_up_uninitialized ("FALSE"),
62+
.read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
63+
.width_byteena_a (1), // Forced value
64+
.numwords_b ( NUMWORDS ),
65+
.numwords_a ( NUMWORDS ),
66+
.widthad_b ( CFG_ABITS ),
67+
.width_b ( CFG_DBITS ),
68+
.widthad_a ( CFG_ABITS ),
69+
.width_a ( CFG_DBITS )
7270
) _TECHMAP_REPLACE_ (
7371
.data_a(B1DATA),
7472
.address_a(B1ADDR),

‎techlibs/intel/common/m9k_bb.v

Lines changed: 25 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -21,27 +21,31 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
2121
q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
2222
addressstall_a, addressstall_b);
2323

24-
parameter clock_enable_input_b = "ALTERNATE";
25-
parameter clock_enable_input_a = "ALTERNATE";
26-
parameter clock_enable_output_b = "NORMAL";
27-
parameter clock_enable_output_a = "NORMAL";
28-
parameter wrcontrol_aclr_a = "NONE";
29-
parameter indata_aclr_a = "NONE";
30-
parameter address_aclr_a = "NONE";
31-
parameter outdata_aclr_a = "NONE";
32-
parameter outdata_reg_a = "UNREGISTERED";
33-
parameter operation_mode = "SINGLE_PORT";
34-
parameter intended_device_family = "MAX 10 FPGA";
35-
parameter outdata_reg_a = "UNREGISTERED";
36-
parameter lpm_type = "altsyncram";
37-
parameter init_type = "unused";
38-
parameter ram_block_type = "AUTO";
39-
parameter numwords_b = 0;
40-
parameter numwords_a = 0;
41-
parameter widthad_b = 1;
42-
parameter width_b = 1;
43-
parameter widthad_a = 1;
44-
parameter width_a = 1;
24+
parameter clock_enable_input_b = "ALTERNATE";
25+
parameter clock_enable_input_a = "ALTERNATE";
26+
parameter clock_enable_output_b = "NORMAL";
27+
parameter clock_enable_output_a = "NORMAL";
28+
parameter wrcontrol_aclr_a = "NONE";
29+
parameter indata_aclr_a = "NONE";
30+
parameter address_aclr_a = "NONE";
31+
parameter outdata_aclr_a = "NONE";
32+
parameter outdata_reg_a = "UNREGISTERED";
33+
parameter operation_mode = "SINGLE_PORT";
34+
parameter intended_device_family = "MAX 10 FPGA";
35+
parameter outdata_reg_a = "UNREGISTERED";
36+
parameter lpm_type = "altsyncram";
37+
parameter init_type = "unused";
38+
parameter ram_block_type = "AUTO";
39+
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
40+
parameter power_up_uninitialized = "FALSE";
41+
parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
42+
parameter width_byteena_a = 1;
43+
parameter numwords_b = 0;
44+
parameter numwords_a = 0;
45+
parameter widthad_b = 1;
46+
parameter width_b = 1;
47+
parameter widthad_a = 1;
48+
parameter width_a = 1;
4549

4650
// Port A declarations
4751
output [35:0] q_a;

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