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FPGA: remove the use of Windows style compiler flags on Windows (oneapi-src#1073)
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57 files changed

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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/CMakeLists.txt

Lines changed: 5 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -13,15 +13,8 @@ else()
1313
message(STATUS "Configuring the design to run on FPGA board ${FPGA_BOARD}")
1414
endif()
1515

16-
# These are Windows-specific flags:
17-
# 1. /EHsc This is a Windows-specific flag that enables exception handling in host code
18-
# 2. /Qactypes Include ac_types headers and link against ac_types emulation libraries
19-
if(WIN32)
20-
set(WIN_FLAG "/EHsc")
21-
set(AC_TYPES_FLAG "/Qactypes")
22-
else()
23-
set(AC_TYPES_FLAG "-qactypes")
24-
endif()
16+
# Include ac_types headers and link against ac_types emulation libraries
17+
set(AC_TYPES_FLAG "-qactypes")
2518

2619
# Allow the user to enable hardware profiling
2720
# Profiling can be enabled when running cmake by adding the flag -DPROFILE_HW=1
@@ -119,9 +112,9 @@ endif()
119112
# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
120113
# 2. The "link" stage invokes the compiler's FPGA backend before linking.
121114
# For this reason, FPGA backend flags must be passed as link flags in CMake.
122-
set(EMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_EMULATOR")
115+
set(EMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} -DFPGA_EMULATOR")
123116
set(EMULATOR_LINK_FLAGS "-fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG}")
124-
set(HARDWARE_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG}")
117+
set(HARDWARE_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} -fintelfpga ${AC_TYPES_FLAG} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG}")
125118
set(REPORT_LINK_FLAGS "-fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xsboard=${FPGA_BOARD} ${FILTER_SIZE_FLAG} ${PIXELS_PER_CYCLE_FLAG} ${MAX_COLS_FLAG} ${PIXEL_BITS_FLAG} ${IP_MODE_FLAG} ${USER_HARDWARE_FLAGS}")
126119
set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}")
127120
# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
@@ -156,4 +149,4 @@ add_custom_target(fpga DEPENDS ${FPGA_TARGET})
156149
set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPILE_FLAGS}")
157150
set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_TARGET}")
158151
# The -reuse-exe flag enables rapid recompilation of host-only code changes.
159-
# See DPC++FPGA/GettingStarted/fast_recompile for details.
152+
# See DPC++FPGA/GettingStarted/fast_recompile for details.

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/anr.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99

1010
#include <CL/sycl.hpp>
1111
#include <sycl/ext/intel/fpga_extensions.hpp>
12-
#include <CL/sycl/INTEL/ac_types/ac_int.hpp>
12+
#include <sycl/ext/intel/ac_types/ac_int.hpp>
1313
#include <limits>
1414
#include <type_traits>
1515
#include <utility>

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/anr_params.hpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33

44
#include <CL/sycl.hpp>
55
#include <sycl/ext/intel/fpga_extensions.hpp>
6-
#include <CL/sycl/INTEL/ac_types/ac_fixed.hpp>
6+
#include <sycl/ext/intel/ac_types/ac_fixed.hpp>
77
#include <iostream>
88
#include <string>
99
#include <utility>
@@ -96,4 +96,4 @@ std::ostream& operator<<(std::ostream& os, const ANRParams& params) {
9696
return os;
9797
}
9898

99-
#endif /* __ANR_PARAMS_HPP__ */
99+
#endif /* __ANR_PARAMS_HPP__ */

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/constants.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
#ifndef __CONSTANTS_HPP__
22
#define __CONSTANTS_HPP__
33

4-
#include <CL/sycl/INTEL/ac_types/ac_int.hpp>
4+
#include <sycl/ext/intel/ac_types/ac_int.hpp>
55

66
// Included from DirectProgramming/DPC++FPGA/include/
77
#include "constexpr_math.hpp"

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/src/qfp.hpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
#include <array>
55
#include <limits>
66

7-
#include <CL/sycl/INTEL/ac_types/ac_int.hpp>
7+
#include <sycl/ext/intel/ac_types/ac_int.hpp>
88

99
// Included from DirectProgramming/DPC++FPGA/include/
1010
#include "constexpr_math.hpp"
@@ -208,4 +208,4 @@ struct QFP {
208208
QFP();
209209
};
210210

211-
#endif /* _QFP_HPP__ */
211+
#endif /* _QFP_HPP__ */

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/src/CMakeLists.txt

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -17,26 +17,20 @@ else()
1717
message(STATUS "Configuring the design to run on FPGA board ${FPGA_BOARD}")
1818
endif()
1919

20-
# This is a Windows-specific flag that enables error handling in host code
21-
if(WIN32)
22-
set(PLATFORM_SPECIFIC_COMPILE_FLAGS "/EHsc /Qactypes /Wall")
23-
set(PLATFORM_SPECIFIC_LINK_FLAGS "/Qactypes")
24-
else()
25-
set(PLATFORM_SPECIFIC_COMPILE_FLAGS "-qactypes -Wformat-security -Werror=format-security -Wall")
26-
set(PLATFORM_SPECIFIC_LINK_FLAGS "")
27-
endif()
20+
# Include ac_types headers and link against ac_types emulation libraries
21+
set(AC_TYPES_FLAG "-qactypes ")
2822

2923
# A DPC++ ahead-of-time (AoT) compile processes the device code in two stages.
3024
# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
3125
# 2. The "link" stage invokes the compiler's FPGA backend before linking.
3226
# For this reason, FPGA backend flags must be passed as link flags in CMake.
33-
set(EMULATOR_COMPILE_FLAGS "${PLATFORM_SPECIFIC_COMPILE_FLAGS} -fintelfpga -DFPGA_EMULATOR")
34-
set(EMULATOR_LINK_FLAGS "-fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}")
35-
set(HARDWARE_COMPILE_FLAGS "${PLATFORM_SPECIFIC_COMPILE_FLAGS} -fintelfpga")
27+
set(EMULATOR_COMPILE_FLAGS "-fintelfpga -DFPGA_EMULATOR -Wformat-security -Werror=format-security -Wall ${AC_TYPES_FLAG}")
28+
set(EMULATOR_LINK_FLAGS "-fintelfpga")
29+
set(HARDWARE_COMPILE_FLAGS "-fintelfpga -Wformat-security -Werror=format-security -Wall ${AC_TYPES_FLAG}")
3630
# By default oneAPI compiler burst interleaves across same memory type,
3731
# -Xsno-interleaving is used to disable burst interleaving and test each memory bank independently
3832
# Refer to https://www.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide/top/flags-attr-prag-ext/optimization-flags/disabl-burst-int.html for more information
39-
set(HARDWARE_LINK_FLAGS "-fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsno-interleaving=default -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS}")
33+
set(HARDWARE_LINK_FLAGS "-fintelfpga -Xshardware -Xsno-interleaving=default -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS}")
4034
# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
4135

4236
###############################################################################

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky/src/CMakeLists.txt

Lines changed: 6 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -14,15 +14,8 @@ else()
1414
message(STATUS "Configuring the design to run on FPGA board ${FPGA_BOARD}")
1515
endif()
1616

17-
# This is a Windows-specific flag that enables error handling in host code
18-
if(WIN32)
19-
set(PLATFORM_SPECIFIC_COMPILE_FLAGS "/EHsc /Qactypes /Wall")
20-
set(PLATFORM_SPECIFIC_LINK_FLAGS "/Qactypes")
21-
else()
22-
set(PLATFORM_SPECIFIC_COMPILE_FLAGS "-qactypes -Wall")
23-
set(PLATFORM_SPECIFIC_LINK_FLAGS "")
24-
endif()
25-
17+
# Include ac_types headers and link against ac_types emulation libraries
18+
set(AC_TYPES_FLAG "-qactypes")
2619

2720
# A10 parameters
2821
set(MATRIX_DIMENSION 32)
@@ -78,10 +71,10 @@ message(STATUS "SEED=${SEED}")
7871
# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
7972
# 2. The "link" stage invokes the compiler's FPGA backend before linking.
8073
# For this reason, FPGA backend flags must be passed as link flags in CMake.
81-
set(EMULATOR_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -fintelfpga -fno-finite-math-only -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR")
82-
set(EMULATOR_LINK_FLAGS "-fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}")
83-
set(HARDWARE_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fintelfpga -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -fp-model=precise -Xsfp-relaxed")
84-
set(HARDWARE_LINK_FLAGS "-fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS} -fp-model=precise -Xsfp-relaxed")
74+
set(EMULATOR_COMPILE_FLAGS "-fintelfpga -Wall ${AC_TYPES_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -fno-finite-math-only -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR")
75+
set(EMULATOR_LINK_FLAGS "-fintelfpga")
76+
set(HARDWARE_COMPILE_FLAGS "-fintelfpga -Wall ${AC_TYPES_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS=${FIXED_ITERATIONS} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -fp-model=precise -Xsfp-relaxed")
77+
set(HARDWARE_LINK_FLAGS "-fintelfpga -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS} -fp-model=precise -Xsfp-relaxed")
8578
# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
8679

8780
###############################################################################

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/cholesky_inversion/src/CMakeLists.txt

Lines changed: 6 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -14,15 +14,8 @@ else()
1414
message(STATUS "Configuring the design to run on FPGA board ${FPGA_BOARD}")
1515
endif()
1616

17-
# This is a Windows-specific flag that enables error handling in host code
18-
if(WIN32)
19-
set(PLATFORM_SPECIFIC_COMPILE_FLAGS "/EHsc /Qactypes /Wall")
20-
set(PLATFORM_SPECIFIC_LINK_FLAGS "/Qactypes")
21-
else()
22-
set(PLATFORM_SPECIFIC_COMPILE_FLAGS "-qactypes -Wall")
23-
set(PLATFORM_SPECIFIC_LINK_FLAGS "")
24-
endif()
25-
17+
# Include ac_types headers and link against ac_types emulation libraries
18+
set(AC_TYPES_FLAG "-qactypes")
2619

2720
# A10 parameters
2821
set(MATRIX_DIMENSION 32)
@@ -87,10 +80,10 @@ message(STATUS "SEED=${SEED}")
8780
# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
8881
# 2. The "link" stage invokes the compiler's FPGA backend before linking.
8982
# For this reason, FPGA backend flags must be passed as link flags in CMake.
90-
set(EMULATOR_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fbracket-depth=512 -fintelfpga -fno-finite-math-only -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR")
91-
set(EMULATOR_LINK_FLAGS "-fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS}")
92-
set(HARDWARE_COMPILE_FLAGS "-Wall ${PLATFORM_SPECIFIC_COMPILE_FLAGS} -Wformat-security -Werror=format-security -fintelfpga -fbracket-depth=512 -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -fp-model=precise -Xsfp-relaxed")
93-
set(HARDWARE_LINK_FLAGS "-fintelfpga ${PLATFORM_SPECIFIC_LINK_FLAGS} -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS} -fp-model=precise -Xsfp-relaxed")
83+
set(EMULATOR_COMPILE_FLAGS "-fintelfpga -Wall ${AC_TYPES_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -fno-finite-math-only -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -DFPGA_EMULATOR")
84+
set(EMULATOR_LINK_FLAGS "-fintelfpga")
85+
set(HARDWARE_COMPILE_FLAGS "-fintelfpga -Wall ${AC_TYPES_FLAG} -Wformat-security -Werror=format-security -fbracket-depth=512 -DFIXED_ITERATIONS_DECOMPOSITION=${FIXED_ITERATIONS_DECOMPOSITION} -DFIXED_ITERATIONS_INVERSION=${FIXED_ITERATIONS_INVERSION} -DCOMPLEX=${COMPLEX} -DMATRIX_DIMENSION=${MATRIX_DIMENSION} -fp-model=precise -Xsfp-relaxed")
86+
set(HARDWARE_LINK_FLAGS "-fintelfpga -Xshardware -Xsclock=${CLOCK_TARGET} -Xsparallel=2 ${SEED} -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS} -fp-model=precise -Xsfp-relaxed")
9487
# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
9588

9689
###############################################################################

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/crr/src/CMakeLists.txt

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -13,11 +13,6 @@ else()
1313
message(STATUS "Configuring the design to run on FPGA board ${FPGA_BOARD}")
1414
endif()
1515

16-
# This is a Windows-specific flag that enables error handling in host code
17-
if(WIN32)
18-
set(WIN_FLAG "/EHsc")
19-
endif()
20-
2116
# Set design parameters according to the selected board
2217
if(FPGA_BOARD MATCHES ".*a10.*")
2318
# A10 parameters
@@ -53,9 +48,9 @@ message(STATUS "OUTER_UNROLL_POW2=${OUTER_UNROLL_POW2}")
5348
# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
5449
# 2. The "link" stage invokes the compiler's FPGA backend before linking.
5550
# For this reason, FPGA backend flags must be passed as link flags in CMake.
56-
set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fintelfpga -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2} -DFPGA_EMULATOR")
51+
set(EMULATOR_COMPILE_FLAGS "-fintelfpga -Wall -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2} -DFPGA_EMULATOR")
5752
set(EMULATOR_LINK_FLAGS "-fintelfpga -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2}")
58-
set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fintelfpga -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2}")
53+
set(HARDWARE_COMPILE_FLAGS "-fintelfpga -Wall -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2}")
5954
set(HARDWARE_LINK_FLAGS "-fintelfpga -Xshardware -Xsdaz -Xsrounding=faithful -Xsparallel=2 ${SEED} -Xsboard=${FPGA_BOARD} -DOUTER_UNROLL=${OUTER_UNROLL} -DINNER_UNROLL=${INNER_UNROLL} -DOUTER_UNROLL_POW2=${OUTER_UNROLL_POW2} ${USER_HARDWARE_FLAGS}")
6055
# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
6156

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/db/src/CMakeLists.txt

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -36,13 +36,8 @@ else()
3636
message(STATUS "Configuring the design to run on FPGA board ${FPGA_BOARD}")
3737
endif()
3838

39-
# This is a Windows-specific flag that enables error handling in host code
40-
if(WIN32)
41-
set(WIN_FLAG "/EHsc")
42-
set(AC_TYPES_FLAG "/Qactypes")
43-
else()
44-
set(AC_TYPES_FLAG "-qactypes")
45-
endif()
39+
# Include ac_types headers and link against ac_types emulation libraries
40+
set(AC_TYPES_FLAG "-qactypes")
4641

4742
# ensure a supported query was requested
4843
if(NOT ${QUERY} EQUAL 1 AND NOT ${QUERY} EQUAL 9 AND NOT ${QUERY} EQUAL 11 AND NOT ${QUERY} EQUAL 12)
@@ -132,11 +127,11 @@ endif()
132127
# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
133128
# 2. The "link" stage invokes the compiler's FPGA backend before linking.
134129
# For this reason, FPGA backend flags must be passed as link flags in CMake.
135-
set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG} -DFPGA_EMULATOR")
130+
set(EMULATOR_COMPILE_FLAGS "-Wall -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG} -DFPGA_EMULATOR")
136131
set(EMULATOR_LINK_FLAGS "-fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}")
137-
set(REPORT_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}")
132+
set(REPORT_COMPILE_FLAGS "-Wall -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}")
138133
set(REPORT_LINK_FLAGS "-fintelfpga -Xshardware -Xsparallel=2 -Xsseed=2 -Xsboard=${FPGA_BOARD} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${USER_HARDWARE_FLAGS}")
139-
set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}")
134+
set(HARDWARE_COMPILE_FLAGS "-Wall -fintelfpga -DQUERY=${QUERY} ${SF_SMALL_ARG} ${AC_TYPES_FLAG}")
140135
set(HARDWARE_LINK_FLAGS "-fintelfpga -Xshardware -Xsparallel=2 ${SEED} -Xsboard=${FPGA_BOARD} -DQUERY=${QUERY} ${SF_SMALL_ARG} ${USER_HARDWARE_FLAGS} ${AC_TYPES_FLAG}")
141136
# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
142137

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt

Lines changed: 6 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -33,15 +33,8 @@ else()
3333
set(ignoreMe "${GZIP}${SNAPPY}")
3434
endif()
3535

36-
# These are Windows-specific flags:
37-
# 1. /EHsc This is a Windows-specific flag that enables exception handling in host code
38-
# 2. /Qactypes Include ac_types headers and link against ac_types emulation libraries
39-
if(WIN32)
40-
set(WIN_FLAG "/EHsc")
41-
set(AC_TYPES_FLAG "/Qactypes")
42-
else()
43-
set(AC_TYPES_FLAG "-qactypes")
44-
endif()
36+
# Include ac_types headers and link against ac_types emulation libraries
37+
set(AC_TYPES_FLAG "-qactypes")
4538

4639
# Allow the user to enable hardware profiling
4740
# Profiling can be enabled when running cmake by adding the flag -DPROFILE_HW=1
@@ -92,11 +85,11 @@ set(CONSTEXPR_STEPS "-fconstexpr-steps=5084968")
9285
# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
9386
# 2. The "link" stage invokes the compiler's FPGA backend before linking.
9487
# For this reason, FPGA backend flags must be passed as link flags in CMake.
95-
set(EMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_EMULATOR")
88+
set(EMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_EMULATOR")
9689
set(EMULATOR_LINK_FLAGS "-fintelfpga ${AC_TYPES_FLAG}")
97-
set(SIMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_SIMULATOR")
90+
set(SIMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_SIMULATOR")
9891
set(SIMULATOR_LINK_FLAGS "-fintelfpga -Xssimulation ${SEED_FLAG} -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS}")
99-
set(HARDWARE_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG}")
92+
set(HARDWARE_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG}")
10093
set(REPORT_LINK_FLAGS "-fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS}")
10194
set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}")
10295
# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
@@ -140,4 +133,4 @@ add_custom_target(fpga DEPENDS ${FPGA_TARGET})
140133
set_target_properties(${FPGA_TARGET} PROPERTIES COMPILE_FLAGS "${HARDWARE_COMPILE_FLAGS}")
141134
set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${FPGA_TARGET}")
142135
# The -reuse-exe flag enables rapid recompilation of host-only code changes.
143-
# See DPC++FPGA/GettingStarted/fast_recompile for details.
136+
# See DPC++FPGA/GettingStarted/fast_recompile for details.

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -28,11 +28,6 @@ else()
2828
message(STATUS "Configuring the design to run on FPGA board ${FPGA_BOARD}")
2929
endif()
3030

31-
# This is a Windows-specific flag that enables error handling in host code
32-
if(WIN32)
33-
set(WIN_FLAG "/EHsc")
34-
endif()
35-
3631
# Set design parameters according to the selected chip
3732
if(FPGA_BOARD MATCHES ".*a10.*")
3833
# A10 parameters
@@ -97,9 +92,9 @@ message(STATUS "NUM_REORDER=${NUM_REORDER}")
9792
# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
9893
# 2. The "link" stage invokes the compiler's FPGA backend before linking.
9994
# For this reason, FPGA backend flags must be passed as link flags in CMake.
100-
set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fintelfpga -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_EMULATOR")
95+
set(EMULATOR_COMPILE_FLAGS "-Wall -fintelfpga -DNUM_ENGINES=${NUM_ENGINES} -DFPGA_EMULATOR")
10196
set(EMULATOR_LINK_FLAGS "-fintelfpga -DNUM_ENGINES=${NUM_ENGINES}")
102-
set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fintelfpga -DNUM_ENGINES=${NUM_ENGINES}")
97+
set(HARDWARE_COMPILE_FLAGS "-Wall -fintelfpga -DNUM_ENGINES=${NUM_ENGINES}")
10398
set(HARDWARE_LINK_FLAGS "-fintelfpga -Xshardware -Xsparallel=2 -Xsopt-arg=\"-nocaching\" -Xsboard=${FPGA_BOARD} -DNUM_ENGINES=${NUM_ENGINES} ${USER_HARDWARE_FLAGS}")
10499
# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
105100

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