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Creating new FPGA tutorial: Autorun (oneapi-src#786)
* New FPGA tutorial: autorun kernels * Formatting * Addressed Mike's comments. * Changing some leftover typos from copying the base template * Clang-format * Small change to output * README update * Addressing Mike's comments * Long path fixes for Windows * Set the SYCL_ENABLE_DEFAULT_CONTEXTS env variable to 1 before running Windows Emulator * Update README with environment variable when running emulator on Windows. * Fix spacing in README Co-authored-by: Mike Tucker <[email protected]>
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‎DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/CMakeLists.txt

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if(UNIX)
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# Direct CMake to use dpcpp rather than the default C++ compiler/linker
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set(CMAKE_CXX_COMPILER dpcpp)
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else() # Windows
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# Force CMake to use dpcpp rather than the default C++ compiler/linker
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# (needed on Windows only)
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include (CMakeForceCompiler)
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CMAKE_FORCE_CXX_COMPILER (dpcpp IntelDPCPP)
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include (Platform/Windows-Clang)
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endif()
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cmake_minimum_required (VERSION 3.4)
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project(Autorun CXX)
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set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
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set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
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set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
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add_subdirectory (src)

‎DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/License.txt

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Copyright Intel Corporation
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SPDX-License-Identifier: MIT
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https://opensource.org/licenses/MIT
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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‎DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/README.md

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# Autorun Kernels
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This FPGA tutorial demonstrates how to create the equivalent of OpenCL 'autorun' kernels in oneAPI. An autorun kernel is one that is submitted before the `main()` function begins, and typically (though not necessarily) never finishes.
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***Documentation***: The [DPC++ FPGA Code Samples Guide](https://software.intel.com/content/www/us/en/develop/articles/explore-dpcpp-through-intel-fpga-code-samples.html) helps you to navigate the samples and build your knowledge of DPC++ for FPGA. <br>
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The [oneAPI DPC++ FPGA Optimization Guide](https://software.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide) is the reference manual for targeting FPGAs through DPC++. <br>
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The [oneAPI Programming Guide](https://software.intel.com/en-us/oneapi-programming-guide) is a general resource for target-independent DPC++ programming.
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| Optimized for | Description
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--- |---
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| OS | Linux* Ubuntu* 18.04/20.04, RHEL*/CentOS* 8, SUSE* 15; Windows* 10
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| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA <br> Intel® FPGA Programmable Acceleration Card (PAC) D5005 (with Intel Stratix® 10 SX) <br> Intel® FPGA 3rd party / custom platforms with oneAPI support <br> *__Note__: Intel® FPGA PAC hardware is only compatible with Ubuntu 18.04*
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| Software | Intel® oneAPI DPC++ Compiler <br> Intel® FPGA Add-On for oneAPI Base Toolkit
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| What you will learn | How and when to use autorun kernels
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| Time to complete | 15 minutes
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## Purpose
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The purpose of this tutorial is to demonstrate how to create autorun kernels in DPCPP. Autorun kernels are submitted to the SYCL queue automatically before `main()` begins and are meant to have no direct interaction with the host. This means that they should not directly access global memory (e.g., via USM pointers or SYCL acccessors) and the host should not wait for them to finish.
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Typically, these kernels are meant to run forever, and data is streamed to and from them using SYCL pipes. This technique is illustrated in the figures below where the middle light-blue kernels (`ARKernel` and `ARForeverKernel`) are autorun kernels, and the dark-blue kernels on the left and right are regular SYCL kernels. The images below correspond to the `Autorun` and `AutorunForever` kernels used in this tutorial. See the comments and code in `autorun.cpp` for more details on the differences.
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<img src="autorun.png" alt="autorun" width="800"/>
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<img src="autorun_forever.png" alt="autorun_forever" width="800"/>
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## Key Concepts
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* How to use the autorun kernel header file (`autorun.hpp`).
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* When it is appropriate to use autorun kernels.
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## License
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Code samples are licensed under the MIT license. See
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[License.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/License.txt) for details.
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Third party program Licenses can be found here: [third-party-programs.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/third-party-programs.txt)
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## Building the `autorun` Tutorial
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### Include Files
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The included header `dpc_common.hpp` is located at `%ONEAPI_ROOT%\dev-utilities\latest\include` on your development system.
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### Running Samples in DevCloud
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If running a sample in the Intel DevCloud, remember that you must specify the type of compute node and whether to run in batch or interactive mode. Compiles to FPGA are only supported on fpga_compile nodes. Executing programs on FPGA hardware is only supported on fpga_runtime nodes of the appropriate type, such as fpga_runtime:arria10 or fpga_runtime:stratix10. Neither compiling nor executing programs on FPGA hardware are supported on the login nodes. For more information, see the Intel® oneAPI Base Toolkit Get Started Guide ([https://devcloud.intel.com/oneapi/documentation/base-toolkit/](https://devcloud.intel.com/oneapi/documentation/base-toolkit/)).
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When compiling for FPGA hardware, it is recommended to increase the job timeout to 12h.
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### Using Visual Studio Code* (Optional)
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You can use Visual Studio Code (VS Code) extensions to set your environment, create launch configurations,
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and browse and download samples.
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The basic steps to build and run a sample using VS Code include:
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- Download a sample using the extension **Code Sample Browser for Intel oneAPI Toolkits**.
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- Configure the oneAPI environment with the extension **Environment Configurator for Intel oneAPI Toolkits**.
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- Open a Terminal in VS Code (**Terminal>New Terminal**).
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- Run the sample in the VS Code terminal using the instructions below.
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To learn more about the extensions and how to configure the oneAPI environment, see
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[Using Visual Studio Code with Intel® oneAPI Toolkits](https://software.intel.com/content/www/us/en/develop/documentation/using-vs-code-with-intel-oneapi/top.html).
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After learning how to use the extensions for Intel oneAPI Toolkits, return to this readme for instructions on how to build and run a sample.
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### On a Linux* System
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1. Generate the `Makefile` by running `cmake`.
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```
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mkdir build
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cd build
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```
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To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command:
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```
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cmake ..
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```
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Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command:
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```
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cmake .. -DFPGA_BOARD=intel_s10sx_pac:pac_s10
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```
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You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command:
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```
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cmake .. -DFPGA_BOARD=<board-support-package>:<board-variant>
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```
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2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow:
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* Compile for emulation (fast compile time, targets emulated FPGA device):
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```
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make fpga_emu
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```
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* Generate the optimization report:
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```
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make report
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```
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* Compile for FPGA hardware (longer compile time, targets FPGA device):
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```
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make fpga
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```
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### On a Windows* System
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1. Generate the `Makefile` by running `cmake`.
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```
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mkdir build
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cd build
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```
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To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command:
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```
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cmake -G "NMake Makefiles" ..
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```
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Alternatively, to compile for the Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX), run `cmake` using the command:
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```
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cmake -G "NMake Makefiles" .. -DFPGA_BOARD=intel_s10sx_pac:pac_s10
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```
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You can also compile for a custom FPGA platform. Ensure that the board support package is installed on your system. Then run `cmake` using the command:
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```
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cmake -G "NMake Makefiles" .. -DFPGA_BOARD=<board-support-package>:<board-variant>
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```
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2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow:
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* Compile for emulation (fast compile time, targets emulated FPGA device):
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```
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nmake fpga_emu
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```
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* Generate the optimization report:
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```
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nmake report
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```
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* Compile for FPGA hardware (longer compile time, targets FPGA device):
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```
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nmake fpga
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```
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*Note:* The Intel® PAC with Intel Arria® 10 GX FPGA and Intel® FPGA PAC D5005 (with Intel Stratix® 10 SX) do not support Windows*. Compiling to FPGA hardware on Windows* requires a third-party or custom Board Support Package (BSP) with Windows* support.<br>
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*Note:* If you encounter any issues with long paths when compiling under Windows*, you may have to create your ‘build’ directory in a shorter path, for example c:\samples\build. You can then run cmake from that directory, and provide cmake with the full path to your sample directory.
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### In Third-Party Integrated Development Environments (IDEs)
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You can compile and run this tutorial in the Eclipse* IDE (in Linux*) and the Visual Studio* IDE (in Windows*). For instructions, refer to the following link: [Intel® oneAPI DPC++ FPGA Workflows on Third-Party IDEs](https://software.intel.com/en-us/articles/intel-oneapi-dpcpp-fpga-workflow-on-ide)
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## Running the Sample
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1. Run the sample on the FPGA emulator (the kernel executes on the CPU):
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```
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./autorun.fpga_emu (Linux)
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set SYCL_ENABLE_DEFAULT_CONTEXTS=1 && autorun.fpga_emu.exe (Windows)
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```
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Note that when running this particular sample in emulation on Windows, an environment variable must be set as shown or the execution will hang.
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2. Run the sample on the FPGA device:
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```
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./autorun.fpga (Linux)
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```
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### Example of Output
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```
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Running the Autorun kernel test
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Running the AutorunForever kernel test
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PASSED
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```

‎DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/autorun.png

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‎DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/autorun.sln

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Microsoft Visual Studio Solution File, Format Version 12.00
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# Visual Studio 15
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VisualStudioVersion = 15.0.28307.705
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MinimumVisualStudioVersion = 10.0.40219.1
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EndProject
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Global
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‎DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/autorun.vcxproj

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‎DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/autorun/autorun_forever.png

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