@@ -70,7 +70,8 @@ LoRaClass::LoRaClass() :
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_frequency(0 ),
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_packetIndex(0 ),
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_implicitHeaderMode(0 ),
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- _onReceive(NULL )
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+ _onReceive(NULL ),
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+ _onTxDone(NULL )
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{
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// overide Stream timeout value
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setTimeout (0 );
@@ -177,13 +178,14 @@ int LoRaClass::beginPacket(int implicitHeader)
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int LoRaClass::endPacket (bool async)
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{
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+
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+ if ((async) && (_onTxDone))
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+ writeRegister (REG_DIO_MAPPING_1, 0x40 ); // DIO0 => TXDONE
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+
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// put in TX mode
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writeRegister (REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX);
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- if (async) {
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- // grace time is required for the radio
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- delayMicroseconds (150 );
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- } else {
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+ if (!async) {
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// wait for TX done
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while ((readRegister (REG_IRQ_FLAGS) & IRQ_TX_DONE_MASK) == 0 ) {
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yield ();
@@ -353,8 +355,24 @@ void LoRaClass::onReceive(void(*callback)(int))
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if (callback) {
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pinMode (_dio0, INPUT);
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+ #ifdef SPI_HAS_NOTUSINGINTERRUPT
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+ SPI.usingInterrupt (digitalPinToInterrupt (_dio0));
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+ #endif
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+ attachInterrupt (digitalPinToInterrupt (_dio0), LoRaClass::onDio0Rise, RISING);
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+ } else {
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+ detachInterrupt (digitalPinToInterrupt (_dio0));
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+ #ifdef SPI_HAS_NOTUSINGINTERRUPT
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+ SPI.notUsingInterrupt (digitalPinToInterrupt (_dio0));
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+ #endif
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+ }
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+ }
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+
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+ void LoRaClass::onTxDone (void (*callback)())
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+ {
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+ _onTxDone = callback;
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- writeRegister (REG_DIO_MAPPING_1, 0x00 );
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+ if (callback) {
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+ pinMode (_dio0, INPUT);
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#ifdef SPI_HAS_NOTUSINGINTERRUPT
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SPI.usingInterrupt (digitalPinToInterrupt (_dio0));
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#endif
@@ -369,6 +387,9 @@ void LoRaClass::onReceive(void(*callback)(int))
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void LoRaClass::receive (int size)
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{
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+
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+ writeRegister (REG_DIO_MAPPING_1, 0x00 ); // DIO0 => RXDONE
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+
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if (size > 0 ) {
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implicitHeaderMode ();
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@@ -640,17 +661,28 @@ void LoRaClass::handleDio0Rise()
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writeRegister (REG_IRQ_FLAGS, irqFlags);
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if ((irqFlags & IRQ_PAYLOAD_CRC_ERROR_MASK) == 0 ) {
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- // received a packet
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- _packetIndex = 0 ;
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- // read packet length
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- int packetLength = _implicitHeaderMode ? readRegister (REG_PAYLOAD_LENGTH) : readRegister (REG_RX_NB_BYTES);
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+ if ((irqFlags & IRQ_RX_DONE_MASK) != 0 ) {
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+ // received a packet
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+ _packetIndex = 0 ;
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- // set FIFO address to current RX address
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- writeRegister (REG_FIFO_ADDR_PTR, readRegister (REG_FIFO_RX_CURRENT_ADDR) );
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+ // read packet length
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+ int packetLength = _implicitHeaderMode ? readRegister (REG_PAYLOAD_LENGTH) : readRegister (REG_RX_NB_BYTES );
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- if (_onReceive) {
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- _onReceive (packetLength);
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+ // set FIFO address to current RX address
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+ writeRegister (REG_FIFO_ADDR_PTR, readRegister (REG_FIFO_RX_CURRENT_ADDR));
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+
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+ if (_onReceive) {
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+ _onReceive (packetLength);
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+ }
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+
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+ // reset FIFO address
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+ writeRegister (REG_FIFO_ADDR_PTR, 0 );
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+ }
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+ else if ((irqFlags & IRQ_TX_DONE_MASK) != 0 ) {
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+ if (_onTxDone) {
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+ _onTxDone ();
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+ }
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}
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}
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}
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