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Pull requests: llvm/circt
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[RTG] Add EmbedValidationValuesPass
RTG
Involving the `rtg` dialect
#8648
opened Jul 3, 2025 by
maerhart
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[Datapath] Operator definitions and canonicalization patterns
#8647
opened Jul 3, 2025 by
cowardsa
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[PyCDE] Improve location information
PyCDE
Python CIRCT Design Entry API
#8635
opened Jul 1, 2025 by
teqdruid
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[FIRRTL] Add "knownlayers" specifications to ExtModules
FIRRTL
Involving the `firrtl` dialect
#8623
opened Jun 30, 2025 by
rwy7
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[FIRRTL] Lower registers under ifdefs
FIRRTL
Involving the `firrtl` dialect
#8605
opened Jun 26, 2025 by
rwy7
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[FIRRTL][CreateSiFiveMetadata] Add memory read-under-write behavior to emitted metadata
#8604
opened Jun 26, 2025 by
fzi-hielscher
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[CMake] Allow Python discovery from virtual environment
#8520
opened May 30, 2025 by
hamidelmaazouz
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[SharedResourcesProblem] [Simplex Scheduler] Simplex scheduler deals with multiple resource constraints
#8480
opened May 13, 2025 by
jiahanxie353
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[SCFToCalyx] Modify top-level function in place and propagate external memory allocations
#8446
opened Apr 25, 2025 by
jiahanxie353
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[ImportVerilog] Convert the unpacked array to a simple bit vector
#8392
opened Apr 4, 2025 by
AnnuCode
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When replacing a register with its reset value, attempt width coercion
FIRRTL
Involving the `firrtl` dialect
#8379
opened Apr 1, 2025 by
rwy7
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Add a few mux-of-const and reg-of-and/or canonicalizers.
FIRRTL
Involving the `firrtl` dialect
#8307
opened Mar 7, 2025 by
rwy7
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[circt-verilog-lsp] Add inlay hints support for Verilog LSP server
#8303
opened Mar 6, 2025 by
uenoku
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