[AArch64][SVE] Fold svmul and svdiv with all-zero operands to zero vector

[k-arrows]

GCC has implemented this in recent patches. Consider the following example.
https://godbolt.org/z/dPY9f3oxe

#include <arm_sve.h>

svint64_t test1 (svbool_t pg, svint64_t op2)
{
  return svmul_x (pg, svdup_s64 (0), op2);
}

svint64_t test2 (svbool_t pg, svint64_t op2)
{
  return svdiv_x (pg, svdup_s64 (0), op2);
}

GCC:

test1(__SVBool_t, __SVInt64_t):
        mov     z0.b, #0
        ret
test2(__SVBool_t, __SVInt64_t):
        mov     z0.b, #0
        ret

Clang:

test1(__SVBool_t, __SVInt64_t):
        mov     z1.d, #0
        mul     z0.d, p0/m, z0.d, z1.d
        ret

test2(__SVBool_t, __SVInt64_t):
        mov     z1.d, #0
        sdivr   z0.d, p0/m, z0.d, z1.d
        ret

I referred to the GCC patch below.
svmul
svdiv

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: None (k-arrows)

GCC has implemented this in recent patches. Consider the following example. https://godbolt.org/z/dPY9f3oxe ```cpp #include <arm_sve.h>

svint64_t test1 (svbool_t pg, svint64_t op2)
{
return svmul_x (pg, svdup_s64 (0), op2);
}

svint64_t test2 (svbool_t pg, svint64_t op2)
{
return svdiv_x (pg, svdup_s64 (0), op2);
}

GCC:
```asm
test1(__SVBool_t, __SVInt64_t):
        mov     z0.b, #<!-- -->0
        ret
test2(__SVBool_t, __SVInt64_t):
        mov     z0.b, #<!-- -->0
        ret

Clang:

test1(__SVBool_t, __SVInt64_t):
        mov     z1.d, #<!-- -->0
        mul     z0.d, p0/m, z0.d, z1.d
        ret

test2(__SVBool_t, __SVInt64_t):
        mov     z1.d, #<!-- -->0
        sdivr   z0.d, p0/m, z0.d, z1.d
        ret

I referred to the GCC patch below.
svmul
svdiv

[paulwalker-arm]

#134116 introduced general simplification support for SVE intrinsics that have an IR instruction equivalent. The PR only covered mul but has since been extended to cover the majority of binops.