[RISCV] Add CodeGen support for Zilsd

[topperc]

I'm working on initial codegen support Zilsd. Focusing on i64 loads/stores in SelectionDAG and f64 loads and stores with Zdinx.

Filing this ticket to increase visibility while I work on the patches.

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Craig Topper (topperc)

I'm working on initial codegen support Zilsd. Focusing on i64 loads/stores in SelectionDAG and f64 loads and stores with Zdinx.

Filing this ticket to increase visibility while I work on the patches.

[lenary]

cc @anmolparalkar-nxp who I think had similar downstream patches against llvm 18 in their branch for some Zilsd support. I don't know how that upstreaming effort is going

Here are some other places that might benefit:

• callee-save spills/reloads two at a time (this was iirc on NXP's branch)
• adding Zilsd in the load/store pairing pass from MIPs (by @djtodoro)

We are interested in more Zilsd support in codegen, so thank you for focussing on this more

[topperc]

I've been referencing this commit: nxp-auto-tools@d677c41#diff-1d077b8beaff531e8d78ba5bb21c368714f270f1b13ba47bb23d5ad2a5d1f01b a bit, but it doesn't use getMemIntrinsicNode or preserve the memory operand.

[topperc]

adding Zilsd in the load/store pairing pass from MIPs (by @djtodoro)

MIPs has separate encoding for both registers. Zilsd requires paired registers which makes this harder.