AArch32 port in assembler does not handle PC offset, causing CREL issues

[aeubanks]

$ cat /tmp/a.cc
void f();

int main() {
        try {
                f();
        } catch (...) {
                return 1;
        }
        return 0;
}
# sysroot required for the following, reproducers attached below
$ clang++ -O2 -shared -o /tmp/nocrel.so /tmp/a.cc -fuse-ld=lld --target=arm-linux-androideabi26
$ clang++ -O2 -shared -o /tmp/crel.so /tmp/a.cc -fuse-ld=lld --target=arm-linux-androideabi26 -Wa,--crel,--allow-experimental-crel
$ llvm-objdump --disassemble /tmp/nocrel.so  > /tmp/nocrel.s
$ llvm-objdump --disassemble /tmp/crel.so  > /tmp/crel.s
$ diff /tmp/nocrel.s /tmp/crel.s
43c43
<      6b4: eb000025            bl      0x750 <_Z1fv@plt>       @ imm = #0x94
---
>      6b4: eb000027            bl      0x758 <_Z1fv@plt+0x8>   @ imm = #0x9c
47,48c47,48
<      6c4: eb000025            bl      0x760 <__cxa_begin_catch@plt> @ imm = #0x94
<      6c8: eb000028            bl      0x770 <__cxa_end_catch@plt> @ imm = #0xa0
---
>      6c4: eb000027            bl      0x768 <__cxa_begin_catch@plt+0x8> @ imm = #0x9c
>      6c8: eb00002a            bl      0x778 <__cxa_end_catch@plt+0x8> @ imm = #0xa8

reproducers

@MaskRay

[MaskRay]

In the CREL mode, PC-relative instructions like bl foo should lead to a R_ARM_CALL relocation referencing foo with an addend of -8 instead of 0.

---

The assembler's ARM port has a limitation where only relocations with implicit addends (REL) are handled.
For CREL, we aim to use explicit addends across all targets to simplify linker/tooling implementation, but this is incompatible with ARMAsmBackend's current design.

To address this issue, we should

• In MCAssembler::evaluateFixup, generalize MCFixupKindInfo::FKF_IsAlignedDownTo32Bits (ARM hack, also used by other backends) to support more fixups, including ARM::fixup_arm_uncondbl (R_ARM_CALL). Create a new hook in MCAsmBackend.
• In ARMAsmBackend, move the Value -= 8 code from adjustFixupValue to the new hook.

unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
...
  case ARM::fixup_arm_condbranch:
  case ARM::fixup_arm_uncondbranch:
  case ARM::fixup_arm_uncondbl:
  case ARM::fixup_arm_condbl:
  case ARM::fixup_arm_blx:
    // Check that the relocation value is legal.
    Value -= 8;
    if (!isInt<26>(Value)) {
      Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
      return 0;

Enabling RELA/CREL support requires significant effort and exceeds my expertise or willingness to address for AArch32.
However, I do want to add a new MCAsmBackend hook to minimize AArch32's invasive modifications to the generic relocation generation framework.

In binutils, the arm-vxworks port introduced RELA support in 2006: https://sourceware.org/pipermail/binutils/2006-March/046211.html

P.S. I recently reviewed MCFixupKindInfo::FKF_IsAlignedDownTo32Bits and planned to address it. This issue is well-timed, allowing me to incorporate it into https://maskray.me/blog/2025-05-26-llvm-integrated-assembler-improving-expressions-and-relocations Thank you!

[llvmbot]

@llvm/issue-subscribers-backend-arm

Author: Arthur Eubanks (aeubanks)

``` $ cat /tmp/a.cc void f();

int main() {
try {
f();
} catch (...) {
return 1;
}
return 0;
}

sysroot required for the following, reproducers attached below

$ clang++ -O2 -shared -o /tmp/nocrel.so /tmp/a.cc -fuse-ld=lld --target=arm-linux-androideabi26
$ clang++ -O2 -shared -o /tmp/crel.so /tmp/a.cc -fuse-ld=lld --target=arm-linux-androideabi26 -Wa,--crel,--allow-experimental-crel
$ llvm-objdump --disassemble /tmp/nocrel.so > /tmp/nocrel.s
$ llvm-objdump --disassemble /tmp/crel.so > /tmp/crel.s
$ diff /tmp/nocrel.s /tmp/crel.s
43c43
< 6b4: eb000025 bl 0x750 <_Z1fv@plt> @ imm = #0x94

> 6b4: eb000027 bl 0x758 <_Z1fv@plt+0x8> @ imm = #0x9c
47,48c47,48
< 6c4: eb000025 bl 0x760 <__cxa_begin_catch@plt> @ imm = #0x94
< 6c8: eb000028 bl 0x770 <__cxa_end_catch@plt> @ imm = #0xa0

> 6c4: eb000027 bl 0x768 <__cxa_begin_catch@plt+0x8> @ imm = #0x9c
> 6c8: eb00002a bl 0x778 <__cxa_end_catch@plt+0x8> @ imm = #0xa8

[reproducers](https://github.com/user-attachments/files/20466956/export.1.zip)

@<!-- -->MaskRay 
</details>

[MaskRay]

• In MCAssembler::evaluateFixup, generalize MCFixupKindInfo::FKF_IsAlignedDownTo32Bits (ARM hack, also used by other backends) to support more fixups, including ARM::fixup_arm_uncondbl (R_ARM_CALL). Create a new hook in MCAsmBackend.

ARM may define the evaluateFixup hook being introduced by #147113