diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 2d635835e3ff7..a31bde85e4d02 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -811,6 +811,7 @@ include "X86SchedSkylakeClient.td"
include "X86SchedSkylakeServer.td"
include "X86SchedIceLake.td"
include "X86SchedAlderlakeP.td"
+include "X86SchedLunarlakeP.td"
include "X86SchedSapphireRapids.td"
//===----------------------------------------------------------------------===//
@@ -1862,10 +1863,12 @@ def : ProcModel<"meteorlake", AlderlakePModel,
ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
def : ProcModel<"arrowlake", AlderlakePModel,
ProcessorFeatures.SRFFeatures, ProcessorFeatures.ADLTuning>;
-foreach P = ["arrowlake-s", "arrowlake_s", "lunarlake"] in {
+foreach P = ["arrowlake-s", "arrowlake_s"] in {
def : ProcModel
;
}
+def : ProcModel<"lunarlake", LunarlakePModel, ProcessorFeatures.ARLSFeatures,
+ ProcessorFeatures.ADLTuning>;
def : ProcModel<"pantherlake", AlderlakePModel,
ProcessorFeatures.PTLFeatures, ProcessorFeatures.ADLTuning>;
def : ProcModel<"clearwaterforest", AlderlakePModel,
diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td
index b31ed81160a29..20d96ffdb482e 100644
--- a/llvm/lib/Target/X86/X86PfmCounters.td
+++ b/llvm/lib/Target/X86/X86PfmCounters.td
@@ -236,6 +236,26 @@ def SapphireRapidsPfmCounters : ProcPfmCounters {
}
def : PfmCountersBinding<"sapphirerapids", SapphireRapidsPfmCounters>;
+def LunarLakePfmCounters : ProcPfmCounters {
+ let CycleCounter = UnhaltedCoreCyclesPfmCounter;
+ let UopsCounter = UopsIssuedPfmCounter;
+ let IssueCounters = [
+ // Refer: https://perfmon-events.intel.com/ section Lunar Lake Hybrid Event
+ // ALU Dispatch - Any of ALUs with latency 1 cycle that is not jmp or Shift.
+ PfmIssueCounter<"LNLPVPort02_03", "uops_dispatched:alu">,
+ PfmIssueCounter<"LNLPPort00_01_02_03_04_05", "uops_dispatched:int_eu_all">,
+ PfmIssueCounter<"LNLPPort00_02_04", "uops_dispatched:jmp">,
+ PfmIssueCounter<"LNLPPort20_21_22", "uops_dispatched:load">,
+ PfmIssueCounter<"LNLPPort01_03_05", "uops_dispatched:shift">,
+ // Slow Dispatch - If uops latency > 1, counted as slow. TBD
+ // PfmIssueCounter<"LNLPPort01_03_05", "uops_dispatched:slow">,
+ PfmIssueCounter<"LNLPPort25_26_27", "uops_dispatched:sta">,
+ PfmIssueCounter<"LNLPPort10_11", "uops_dispatched:std">
+ ];
+ let ValidationCounters = DefaultIntelPfmValidationCounters;
+}
+def : PfmCountersBinding<"Lunarlake", LunarLakePfmCounters>;
+
// AMD X86 Counters.
defvar DefaultAMDPfmValidationCounters = [
PfmValidationCounter,
diff --git a/llvm/lib/Target/X86/X86SchedLunarlakeP.td b/llvm/lib/Target/X86/X86SchedLunarlakeP.td
new file mode 100644
index 0000000000000..e82d7ab805077
--- /dev/null
+++ b/llvm/lib/Target/X86/X86SchedLunarlakeP.td
@@ -0,0 +1,2409 @@
+//=----- X86SchedLunarlakeP.td - X86 LunarlakeP Scheduling *- tablegen -----*=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for LunarlakeP to support instruction
+// scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+def LunarlakePModel : SchedMachineModel {
+ // LunarlakeP can allocate 8 uops per cycle.
+ // Max micro-ops that may be scheduled per cycle.
+ // Based on Allocator Width
+ let IssueWidth = 8;
+ // Max micro-ops that can be buffered.
+ // Based on size of ROB
+ let MicroOpBufferSize = 792;
+ // INT LOAD takes 4 cycles
+ let LoadLatency = 4;
+ let MispredictPenalty = 14;
+ // Latency for microcoded instructions or instructions without latency info.
+ int MaxLatency = 100;
+ // Based on the LSD (loop-stream detector) queue size (ST).
+ // LSD is 200 uops per logical processor in single threaded mode
+ // For SMT 100 uops/thread, LionCove removed SMT in HW.
+ let LoopMicroOpBufferSize = 200;
+ // This flag is set to allow the scheduler to assign a default model to
+ // unrecognized opcodes.
+ let CompleteModel = 0;
+}
+
+let SchedModel = LunarlakePModel in {
+
+// LunarlakeP can issue micro-ops to 18 different ports in one cycle.
+// Lion Cove architectural spec uses port naming that is not sequential
+// for better comprehension we opt for sequential naming since this ports
+// serve logical information for schedule only.
+// 6 INT ALU Ports {P0 to P5}
+def LNLPPort00 : ProcResource<1>;
+def LNLPPort01 : ProcResource<1>;
+def LNLPPort02 : ProcResource<1>;
+def LNLPPort03 : ProcResource<1>;
+def LNLPPort04 : ProcResource<1>;
+def LNLPPort05 : ProcResource<1>;
+// 4 VEC ALU Ports {V0 to V3}
+def LNLPVPort00 : ProcResource<1>;
+def LNLPVPort01 : ProcResource<1>;
+def LNLPVPort02 : ProcResource<1>;
+def LNLPVPort03 : ProcResource<1>;
+// 2 Store Data Ports {P10 to P11}
+def LNLPPort10 : ProcResource<1>;
+def LNLPPort11 : ProcResource<1>;
+// 6 MEM Ports 6 AGU shared with 3 LD, 3 ST
+// AGU LD {P20 to P22}
+def LNLPPort20 : ProcResource<1>;
+def LNLPPort21 : ProcResource<1>;
+def LNLPPort22 : ProcResource<1>;
+// AGU ST {P25 to P27}
+def LNLPPort25 : ProcResource<1>;
+def LNLPPort26 : ProcResource<1>;
+def LNLPPort27 : ProcResource<1>;
+
+// Workaround to represent invalid ports. WriteRes shouldn't use this resource.
+def LNLPPortInvalid :ProcResource<1>;
+
+// Many micro-ops are capable of issuing on multiple ports.
+def LNLPVPort00_01 : ProcResGroup<[LNLPVPort00, LNLPVPort01]>;
+def LNLPVPort02_03 : ProcResGroup<[LNLPVPort02, LNLPVPort03]>;
+def LNLPPort00_02_04 : ProcResGroup<[LNLPPort00, LNLPPort02, LNLPPort04]>;
+def LNLPPort01_03_05 : ProcResGroup<[LNLPPort01, LNLPPort03, LNLPPort05]>;
+def LNLPPort20_21_22 : ProcResGroup<[LNLPPort20, LNLPPort21, LNLPPort22]>;
+def LNLPPort25_26_27 : ProcResGroup<[LNLPPort25, LNLPPort26, LNLPPort27]>;
+
+// INT EU has 112 reservation stations.
+def LNLPPort00_01_02_03_04_05 : ProcResGroup<[LNLPPort00, LNLPPort01, LNLPPort02,
+ LNLPPort03, LNLPPort04, LNLPPort05]>{
+ let BufferSize = 110; // Reduced from 128 in GLC
+}
+
+// VEC EU has 180 reservation stations.
+def LNLPVPort00_01_02_03 : ProcResGroup<[LNLPVPort00, LNLPVPort01, LNLPVPort02,
+ LNLPVPort03]>{
+ let BufferSize = 180; // EU for INT and VEC are seperated
+ // VEC QUEUE SIZE = 60 + VEC EU RS (60+60)
+}
+// STD has 48 reservation stations.
+def LNLPPort10_11 : ProcResGroup<[LNLPPort10, LNLPPort11]> {
+ let BufferSize = 48;
+}
+
+// MEM has 72 reservation stations.
+def LNLPPort20_21_22_25_26_27 : ProcResGroup<[LNLPPort20, LNLPPort21, LNLPPort22,
+ LNLPPort25, LNLPPort26, LNLPPort27]> {
+ let BufferSize = 72;
+}
+
+def LNLPPortAny : ProcResGroup<[LNLPPort00, LNLPPort01, LNLPPort02, LNLPPort03,
+ LNLPPort04, LNLPPort05, LNLPVPort00, LNLPVPort01,
+ LNLPVPort02, LNLPVPort03, LNLPPort10, LNLPPort11,
+ LNLPPort20, LNLPPort21, LNLPPort22, LNLPPort25,
+ LNLPPort26, LNLPPort27]>;
+
+// Integer loads are 4 cycles, so ReadAfterLd registers needn't be available
+// until 4 cycles after the memory operand.
+def : ReadAdvance;
+
+// TODO: 6 Cycle latency for Vec load comes from ADL
+// Vector loads are 6 cycles, so ReadAfterVec*Ld registers needn't be available
+// until 6 cycles after the memory operand.
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+
+def : ReadAdvance;
+
+// Many SchedWrites are defined in pairs with and without a folded load.
+// Instructions with folded loads are usually micro-fused, so they only appear
+// as two micro-ops when queued in the reservation station.
+// This multiclass defines the resource usage for variants with and without
+// folded loads.
+multiclass LNLPWriteResPair ExePorts,
+ int Lat, list Res = [1], int UOps = 1,
+ int LoadLat = 4, int LoadUOps = 1> {
+ // Register variant is using a single cycle on ExePort.
+ def : WriteRes {
+ let Latency = Lat;
+ let ReleaseAtCycles = Res;
+ let NumMicroOps = UOps;
+ }
+
+ // Memory variant also uses a cycle on port 20/21/22 and adds LoadLat cycles to
+ // the latency (default = 4).
+ def : WriteRes {
+ let Latency = !add(Lat, LoadLat);
+ let ReleaseAtCycles = !listconcat([1], Res);
+ let NumMicroOps = !add(UOps, LoadUOps);
+ }
+}
+
+defm : X86WriteResUnsupported;
+
+//===----------------------------------------------------------------------===//
+// The following definitons are infered by smg.
+//===----------------------------------------------------------------------===//
+
+def : WriteRes;
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 3;
+}
+defm : X86WriteRes;
+defm : X86WriteResPairUnsupported;
+defm : X86WriteResPairUnsupported;
+def : WriteRes;
+def : WriteRes {
+ let Latency = 11;
+}
+defm : X86WriteRes;
+def : WriteRes;
+defm : X86WriteRes;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+def : WriteRes;
+defm : X86WriteRes;
+defm : LNLPWriteResPair;
+def : WriteRes;
+def : WriteRes {
+ let Latency = 11;
+}
+defm : X86WriteRes;
+def : WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+
+def : WriteRes;
+defm : X86WriteRes;
+def : WriteRes;
+defm : X86WriteRes;
+
+defm : LNLPWriteResPair;
+def : WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [1, 4];
+ let Latency = 5;
+}
+defm : X86WriteRes;
+defm : X86WriteRes;
+
+def : WriteRes {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3, 4];
+ let Latency = 7;
+}
+
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+defm : LNLPWriteResPair;
+defm : X86WriteResPairUnsupported;
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : X86WriteResPairUnsupported;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : X86WriteResPairUnsupported;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported;
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteResUnsupported;
+defm : X86WriteResUnsupported;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+defm : X86WriteRes;
+defm : X86WriteRes;
+//defm : X86WriteRes;
+// FIXME: Incompleted schedwrite.
+//defm : X86WriteResUnsupported;
+defm : LNLPWriteResPair;
+//defm : X86WriteRes;
+// FIXME: Incompleted schedwrite.
+//defm : X86WriteResUnsupported;
+defm : LNLPWriteResPair;
+
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+def : WriteRes {
+ let Latency = 2;
+}
+// FIXME: Latency
+defm : X86WriteRes; // 8
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : X86WriteResPairUnsupported;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : X86WriteResPairUnsupported;
+def : WriteRes;
+defm : X86WriteRes;
+def : WriteRes;
+defm : X86WriteRes;
+def : WriteRes {
+ let Latency = 3;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes;
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+defm : X86WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [7];
+ let Latency = 7;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [7, 6];
+ let Latency = 13;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10, 6];
+ let Latency = 16;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10, 6];
+ let Latency = 16;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10, 7];
+ let Latency = 17;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [7];
+ let Latency = 7;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [7, 6];
+ let Latency = 13;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [7];
+ let Latency = 7;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [7, 7];
+ let Latency = 14;
+}
+defm : X86WriteResPairUnsupported;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+def : WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+
+def : WriteRes {
+ let Latency = 7;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [6];
+ let Latency = 7;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [7];
+ let Latency = 8;
+}
+def : WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [1, 6];
+ let Latency = 7;
+}
+def : WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [1, 7];
+ let Latency = 8;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteResUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3, 7];
+ let Latency = 10;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [3, 7];
+ let Latency = 10;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported;
+
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : X86WriteResPairUnsupported;
+def : WriteRes;
+def : WriteRes {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10, 6];
+ let Latency = 16;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [15];
+ let Latency = 15;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [15, 6];
+ let Latency = 21;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [15];
+ let Latency = 15;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [15, 6];
+ let Latency = 21;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [15];
+ let Latency = 15;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [15, 7];
+ let Latency = 22;
+}
+defm : X86WriteResPairUnsupported;
+def : WriteRes {
+ let ReleaseAtCycles = [7, 1];
+ let Latency = 21;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10, 6];
+ let Latency = 16;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes {
+ let ReleaseAtCycles = [10, 7];
+ let Latency = 17;
+}
+defm : X86WriteResPairUnsupported;
+defm : X86WriteRes;
+defm : X86WriteResUnsupported;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : X86WriteRes;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : X86WriteResPairUnsupported;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : LNLPWriteResPair;
+defm : X86WriteResPairUnsupported;
+defm : X86WriteRes