@@ -81,8 +81,7 @@ struct XAigerWriter
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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- vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int >> ci_bits;
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- vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int ,int >> co_bits;
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+ vector<SigBit> ci_bits, co_bits;
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dict<SigBit, float > arrival_times;
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vector<pair<int , int >> aig_gates;
@@ -367,7 +366,6 @@ struct XAigerWriter
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cell->setPort (port_name, rhs);
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}
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- int offset = 0 ;
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for (auto b : rhs.bits ()) {
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SigBit I = sigmap (b);
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if (b == RTLIL::Sx)
@@ -378,7 +376,7 @@ struct XAigerWriter
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else
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alias_map[b] = I;
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}
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- co_bits.emplace_back (b, cell, port_name, offset++, 0 );
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+ co_bits.emplace_back (b);
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unused_bits.erase (b);
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}
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}
@@ -398,9 +396,8 @@ struct XAigerWriter
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cell->setPort (port_name, rhs);
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}
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- int offset = 0 ;
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for (const auto &b : rhs.bits ()) {
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- ci_bits.emplace_back (b, cell, port_name, offset++ );
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+ ci_bits.emplace_back (b);
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SigBit O = sigmap (b);
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if (O != b)
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alias_map[O] = b;
@@ -487,15 +484,13 @@ struct XAigerWriter
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aig_map[bit] = 2 *aig_m;
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}
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- for (auto &c : ci_bits) {
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- RTLIL::SigBit bit = std::get<0 >(c);
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+ for (auto bit : ci_bits) {
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aig_m++, aig_i++;
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aig_map[bit] = 2 *aig_m;
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}
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- for (auto &c : co_bits) {
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- RTLIL::SigBit bit = std::get<0 >(c);
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- std::get<4 >(c) = ordered_outputs[bit] = aig_o++;
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+ for (auto bit : co_bits) {
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+ ordered_outputs[bit] = aig_o++;
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aig_outputs.push_back (bit2aig (bit));
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}
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@@ -508,7 +503,6 @@ struct XAigerWriter
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ordered_outputs[bit] = aig_o++;
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aig_outputs.push_back (bit2aig (bit));
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}
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-
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}
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void write_aiger (std::ostream &f, bool ascii_mode)
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