Merge pull request YosysHQ#1571 from YosysHQ/eddie/fix_1570

eddiehung · web-flow · commit d675f22f4e41 · 2019-12-19T12:21:22.000-05:00
mem_arst.v: do not redeclare ANSI port
diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v
@@ -7,11 +7,9 @@ module MyMem #(
   input                  Clk_i,
   input  [AddrWidth-1:0] Addr_i,
   input  [DataWidth-1:0] Data_i,
-  output [DataWidth-1:0] Data_o,
+  output reg [DataWidth-1:0] Data_o,
   input                  WR_i);
 
-  reg [DataWidth-1:0] Data_o;
-
   localparam Size = 2**AddrWidth;
 
   (* mem2reg *)
