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mmahadevan108MaureenHelm
mmahadevan108
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MaureenHelm
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MXRT600: Update driver files to SDK release 2.8.2
Update MXRT600 drivers to SDK 2.8.2 Origin: MCUXpresso SDK License: BSD 3-Clause URL: mcux.nxp.com Maintained-by: External Signed-off-by: Mahesh Mahadevan <[email protected]>
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lines changed

‎mcux/drivers/imxrt6xx/fsl_acmp.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
3-
* Copyright 2016-2019 NXP
3+
* Copyright 2016-2020 NXP
44
* All rights reserved.
55
*
66
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,12 +22,12 @@
2222

2323
/*! @name Driver version */
2424
/*@{*/
25-
/*! @brief ACMP driver version 2.0.5. */
26-
#define FSL_ACMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 5U))
25+
/*! @brief ACMP driver version 2.0.6. */
26+
#define FSL_ACMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 6U))
2727
/*@}*/
2828

2929
/*! @brief The mask of status flags cleared by writing 1. */
30-
#define CMP_C0_CFx_MASK (CMP_C0_CFR_MASK | CMP_C0_CFF_MASK)
30+
#define CMP_C0_CFx_MASK (CMP_C0_CFR_MASK | CMP_C0_CFF_MASK)
3131
#define CMP_C1_CHNn_MASK 0xFF0000U /* C1_CHN0 - C1_CHN7. */
3232
#define CMP_C2_CHnF_MASK 0xFF0000U /* C2_CH0F - C2_CH7F. */
3333

@@ -151,7 +151,7 @@ typedef struct _acmp_filter_config
151151
typedef struct _acmp_dac_config
152152
{
153153
acmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
154-
uint32_t DACValue; /*!< Value for DAC Output Voltage. Available range is 0-63. */
154+
uint32_t DACValue; /*!< Value for DAC Output Voltage. Available range is 0-255. */
155155

156156
#if defined(FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT) && (FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT == 1U)
157157
bool enableOutput; /*!< Enable the DAC output. */

‎mcux/drivers/imxrt6xx/fsl_cache.c

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2016-2019 NXP
2+
* Copyright 2016-2020 NXP
33
* All rights reserved.
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
@@ -71,7 +71,7 @@ uint32_t CACHE64_GetInstanceByAddr(uint32_t address)
7171

7272
for (i = 0; i < ARRAY_SIZE(s_cache64ctrlBases); i++)
7373
{
74-
if (address >= s_cache64PhymemBases[i] && address < s_cache64PhymemBases[i] + s_cache64PhymemSizes[i])
74+
if ((address >= s_cache64PhymemBases[i]) && (address < s_cache64PhymemBases[i] + s_cache64PhymemSizes[i]))
7575
{
7676
break;
7777
}
@@ -103,17 +103,17 @@ status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config)
103103
CLOCK_EnableClock(s_cache64Clocks[instance]);
104104
#endif
105105

106-
for (i = 0; i < CACHE64_REGION_NUM - 1; i++)
106+
for (i = 0; i < CACHE64_REGION_NUM - 1U; i++)
107107
{
108-
assert((config->boundaryAddr[i] & (CACHE64_REGION_ALIGNMENT - 1)) == 0);
109-
*(topReg + i) = config->boundaryAddr[i] >= CACHE64_REGION_ALIGNMENT ?
110-
config->boundaryAddr[i] - CACHE64_REGION_ALIGNMENT :
111-
0U;
108+
assert((config->boundaryAddr[i] & (CACHE64_REGION_ALIGNMENT - 1U)) == 0U);
109+
((volatile uint32_t *)topReg)[i] = config->boundaryAddr[i] >= CACHE64_REGION_ALIGNMENT ?
110+
config->boundaryAddr[i] - CACHE64_REGION_ALIGNMENT :
111+
0U;
112112
}
113113

114114
for (i = 0; i < CACHE64_REGION_NUM; i++)
115115
{
116-
polsel |= (((uint32_t)config->policy[i]) << (2 * i));
116+
polsel |= (((uint32_t)config->policy[i]) << (2U * i));
117117
}
118118
base->POLSEL = polsel;
119119

@@ -130,7 +130,7 @@ status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config)
130130
*/
131131
void CACHE64_GetDefaultConfig(cache64_config_t *config)
132132
{
133-
memset(config, 0, sizeof(cache64_config_t));
133+
(void)memset(config, 0, sizeof(cache64_config_t));
134134

135135
config->boundaryAddr[0] = s_cache64PhymemSizes[0];
136136
config->policy[0] = kCACHE64_PolicyWriteBack;
@@ -172,7 +172,7 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base)
172172
base->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
173173

174174
/* Wait until the cache command completes. */
175-
while (base->CCR & CACHE64_CTRL_CCR_GO_MASK)
175+
while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
176176
{
177177
}
178178

@@ -195,7 +195,7 @@ void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
195195
uint32_t endAddr = address + size_byte;
196196
uint32_t pccReg = 0;
197197
/* Align address to cache line size. */
198-
uint32_t startAddr = address & ~(CACHE64_LINESIZE_BYTE - 1U);
198+
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
199199
uint32_t instance = CACHE64_GetInstanceByAddr(address);
200200
uint32_t endLim;
201201
CACHE64_CTRL_Type *base;
@@ -218,10 +218,10 @@ void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
218218
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
219219

220220
/* Wait until the cache command completes. */
221-
while (base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK)
221+
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
222222
{
223223
}
224-
startAddr += CACHE64_LINESIZE_BYTE;
224+
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
225225
}
226226
}
227227

@@ -235,7 +235,7 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base)
235235
base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
236236

237237
/* Wait until the cache command completes. */
238-
while (base->CCR & CACHE64_CTRL_CCR_GO_MASK)
238+
while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
239239
{
240240
}
241241

@@ -258,7 +258,7 @@ void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte)
258258
uint32_t endAddr = address + size_byte;
259259
uint32_t pccReg = 0;
260260
/* Align address to cache line size. */
261-
uint32_t startAddr = address & ~(CACHE64_LINESIZE_BYTE - 1U);
261+
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
262262
uint32_t instance = CACHE64_GetInstanceByAddr(address);
263263
uint32_t endLim;
264264
CACHE64_CTRL_Type *base;
@@ -281,10 +281,10 @@ void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte)
281281
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
282282

283283
/* Wait until the cache command completes. */
284-
while (base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK)
284+
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
285285
{
286286
}
287-
startAddr += CACHE64_LINESIZE_BYTE;
287+
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
288288
}
289289
}
290290

@@ -299,7 +299,7 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base)
299299
CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
300300

301301
/* Wait until the cache command completes. */
302-
while (base->CCR & CACHE64_CTRL_CCR_GO_MASK)
302+
while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
303303
{
304304
}
305305

@@ -323,7 +323,7 @@ void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
323323
uint32_t endAddr = address + size_byte;
324324
uint32_t pccReg = 0;
325325
/* Align address to cache line size. */
326-
uint32_t startAddr = address & ~(CACHE64_LINESIZE_BYTE - 1U);
326+
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
327327
uint32_t instance = CACHE64_GetInstanceByAddr(address);
328328
uint32_t endLim;
329329
CACHE64_CTRL_Type *base;
@@ -346,10 +346,10 @@ void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
346346
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
347347

348348
/* Wait until the cache command completes. */
349-
while (base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK)
349+
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
350350
{
351351
}
352-
startAddr += CACHE64_LINESIZE_BYTE;
352+
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
353353
}
354354
}
355355

‎mcux/drivers/imxrt6xx/fsl_cache.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2016-2019 NXP
2+
* Copyright 2016-2020 NXP
33
* All rights reserved.
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
@@ -21,14 +21,14 @@
2121

2222
/*! @name Driver version */
2323
/*@{*/
24-
/*! @brief cache driver version 2.0.1. */
25-
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
24+
/*! @brief cache driver version 2.0.2. */
25+
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
2626
/*@}*/
2727

2828
/*! @brief cache line size. */
2929
#define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
3030
/*! @brief cache region number. */
31-
#define CACHE64_REGION_NUM (3)
31+
#define CACHE64_REGION_NUM (3U)
3232
/*! @brief cache region alignment. */
3333
#define CACHE64_REGION_ALIGNMENT (0x400U)
3434

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