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LPC55S69: Update device files to SDK 2.8.2
Update LPC55S69 to SDK 2.8.2 Origin: MCUXpresso SDK License: BSD 3-Clause URL: mcux.nxp.com Maintained-by: External Signed-off-by: Mahesh Mahadevan <[email protected]>
1 parent b895779 commit 7d42c21

14 files changed

+23030
-30109
lines changed

‎mcux/devices/LPC55S69/LPC55S69_cm33_core0.h

Lines changed: 11342 additions & 14840 deletions
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‎mcux/devices/LPC55S69/LPC55S69_cm33_core0.xml

Lines changed: 45 additions & 95 deletions
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‎mcux/devices/LPC55S69/LPC55S69_cm33_core0_features.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
11
/*
22
** ###################################################################
33
** Version: rev. 1.1, 2019-05-16
4-
** Build: b190719
4+
** Build: b200401
55
**
66
** Abstract:
77
** Chip specific module features.
88
**
99
** Copyright 2016 Freescale Semiconductor, Inc.
10-
** Copyright 2016-2019 NXP
10+
** Copyright 2016-2020 NXP
1111
** All rights reserved.
1212
**
1313
** SPDX-License-Identifier: BSD-3-Clause
@@ -75,7 +75,7 @@
7575
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
7676
/* @brief PUF availability on the SoC. */
7777
#define FSL_FEATURE_SOC_PUF_COUNT (1)
78-
/* @brief RNG1 availability on the SoC. */
78+
/* @brief LPC_RNG1 availability on the SoC. */
7979
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
8080
/* @brief RTC availability on the SoC. */
8181
#define FSL_FEATURE_SOC_RTC_COUNT (1)
@@ -146,6 +146,8 @@
146146
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
147147
/* @brief Temperature sensor parameter Alpha. */
148148
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
149+
/* @brief the buffer size of temperature sensor. */
150+
#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
149151

150152
/* CASPER module features */
151153

@@ -319,8 +321,6 @@
319321

320322
/* SYSCON module features */
321323

322-
/* @brief Pointer to ROM IAP entry functions */
323-
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
324324
/* @brief Flash page size in bytes */
325325
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
326326
/* @brief Flash sector size in bytes */

‎mcux/devices/LPC55S69/LPC55S69_cm33_core1.h

Lines changed: 11342 additions & 14840 deletions
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‎mcux/devices/LPC55S69/LPC55S69_cm33_core1.xml

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‎mcux/devices/LPC55S69/LPC55S69_cm33_core1_features.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
11
/*
22
** ###################################################################
33
** Version: rev. 1.1, 2019-05-16
4-
** Build: b190719
4+
** Build: b200401
55
**
66
** Abstract:
77
** Chip specific module features.
88
**
99
** Copyright 2016 Freescale Semiconductor, Inc.
10-
** Copyright 2016-2019 NXP
10+
** Copyright 2016-2020 NXP
1111
** All rights reserved.
1212
**
1313
** SPDX-License-Identifier: BSD-3-Clause
@@ -75,7 +75,7 @@
7575
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
7676
/* @brief PUF availability on the SoC. */
7777
#define FSL_FEATURE_SOC_PUF_COUNT (1)
78-
/* @brief RNG1 availability on the SoC. */
78+
/* @brief LPC_RNG1 availability on the SoC. */
7979
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
8080
/* @brief RTC availability on the SoC. */
8181
#define FSL_FEATURE_SOC_RTC_COUNT (1)
@@ -146,6 +146,8 @@
146146
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
147147
/* @brief Temperature sensor parameter Alpha. */
148148
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
149+
/* @brief the buffer size of temperature sensor. */
150+
#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
149151

150152
/* CASPER module features */
151153

@@ -319,8 +321,6 @@
319321

320322
/* SYSCON module features */
321323

322-
/* @brief Pointer to ROM IAP entry functions */
323-
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
324324
/* @brief Flash page size in bytes */
325325
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
326326
/* @brief Flash sector size in bytes */

‎mcux/devices/LPC55S69/fsl_clock.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2017 - 2019 , NXP
2+
* Copyright 2017 - 2020 , NXP
33
* All rights reserved.
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
@@ -1478,8 +1478,8 @@ uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup)
14781478
/* Get the input clock frequency of PLL. */
14791479
clkRate = CLOCK_GetPLL0InClockRate();
14801480

1481-
if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) &&
1482-
((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) &&
1481+
if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) &&
1482+
((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) &&
14831483
((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) &&
14841484
((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL))
14851485
{

‎mcux/devices/LPC55S69/fsl_clock.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2017 - 2019 , NXP
2+
* Copyright 2017 - 2020, NXP
33
* All rights reserved.
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
@@ -21,8 +21,8 @@
2121

2222
/*! @name Driver version */
2323
/*@{*/
24-
/*! @brief CLOCK driver version 2.3.1. */
25-
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
24+
/*! @brief CLOCK driver version 2.3.2. */
25+
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
2626
/*@}*/
2727

2828
/*! @brief Configure whether driver controls clock
@@ -716,7 +716,7 @@ extern "C" {
716716

717717
/**
718718
* @brief Enable the clock for specific IP.
719-
* @param name : Clock to be enabled.
719+
* @param clk : Clock to be enabled.
720720
* @return Nothing
721721
*/
722722
static inline void CLOCK_EnableClock(clock_ip_name_t clk)
@@ -726,7 +726,7 @@ static inline void CLOCK_EnableClock(clock_ip_name_t clk)
726726
}
727727
/**
728728
* @brief Disable the clock for specific IP.
729-
* @param name : Clock to be Disabled.
729+
* @param clk : Clock to be Disabled.
730730
* @return Nothing
731731
*/
732732
static inline void CLOCK_DisableClock(clock_ip_name_t clk)
@@ -738,7 +738,7 @@ static inline void CLOCK_DisableClock(clock_ip_name_t clk)
738738
* @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
739739
* Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
740740
* enabled.
741-
* @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
741+
* @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
742742
* @return returns success or fail status.
743743
*/
744744
status_t CLOCK_SetupFROClocking(uint32_t iFreq);
@@ -804,7 +804,7 @@ void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
804804
/**
805805
* @brief Set the flexcomm output frequency.
806806
* @param id : flexcomm instance id
807-
* freq : output frequency
807+
* @param freq : output frequency
808808
* @return 0 : the frequency range is out of range.
809809
* 1 : switch successfully.
810810
*/

‎mcux/devices/LPC55S69/fsl_power.h

Lines changed: 29 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ typedef enum pd_bits
7171
kPDRUNCFG_ForceUnsigned = 0x80000000U,
7272
} pd_bit_t;
7373

74-
/*@brief BOD VBAT level */
74+
/*! @brief BOD VBAT level */
7575
typedef enum _power_bod_vbat_level
7676
{
7777
kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */
@@ -102,7 +102,7 @@ typedef enum _power_bod_vbat_level
102102
kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */
103103
} power_bod_vbat_level_t;
104104

105-
/*@brief BOD Hysteresis control */
105+
/*! @brief BOD Hysteresis control */
106106
typedef enum _power_bod_hyst
107107
{
108108
kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */
@@ -111,7 +111,7 @@ typedef enum _power_bod_hyst
111111
kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */
112112
} power_bod_hyst_t;
113113

114-
/*@brief BOD core level */
114+
/*! @brief BOD core level */
115115
typedef enum _power_bod_core_level
116116
{
117117
kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */
@@ -293,6 +293,27 @@ typedef enum _power_bod_core_level
293293
#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \
294294
(1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */
295295

296+
#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \
297+
(16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/
298+
#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \
299+
(17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */
300+
#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \
301+
(18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */
302+
#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \
303+
(19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */
304+
#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \
305+
(1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \
306+
disable/enable mask, 0: disable, 1: enable */
307+
#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \
308+
(1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \
309+
disable/enable mask, 0: disable, 1: enable */
310+
#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \
311+
(1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \
312+
disable/enable mask, 0: disable, 1: enable */
313+
#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \
314+
(1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \
315+
disable/enable mask, 0: disable, 1: enable */
316+
296317
#ifdef __cplusplus
297318
extern "C" {
298319
#endif
@@ -359,7 +380,6 @@ static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod
359380
/*!
360381
* @brief API to enable deep sleep bit in the ARM Core.
361382
*
362-
* @param none
363383
* @return none
364384
*/
365385
static inline void POWER_EnableDeepSleep(void)
@@ -370,7 +390,6 @@ static inline void POWER_EnableDeepSleep(void)
370390
/*!
371391
* @brief API to disable deep sleep bit in the ARM Core.
372392
*
373-
* @param none
374393
* @return none
375394
*/
376395
static inline void POWER_DisableDeepSleep(void)
@@ -383,7 +402,7 @@ static inline void POWER_DisableDeepSleep(void)
383402
* This MUST BE EXECUTED outside the Flash:
384403
* either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is
385404
* preferable to have all functions defined in this file implemented in ROM.
386-
* @param None
405+
*
387406
* @return Nothing
388407
*/
389408
void POWER_CycleCpuAndFlash(void);
@@ -481,17 +500,16 @@ void POWER_SetVoltageForFreq(uint32_t system_freq_hz);
481500
/*!
482501
* @brief Power Library API to return the library version.
483502
*
484-
* @param none
485503
* @return version number of the power library
486504
*/
487505
uint32_t POWER_GetLibVersion(void);
488506

489507
/**
490508
* @brief Sets board-specific trim values for 16MHz XTAL
491-
* @param pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
492-
* @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
509+
* @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
510+
* @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
493511
* becomes 120
494-
* @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
512+
* @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
495513
* becomes 120
496514
* @return none
497515
* @note Following default Values can be used:
@@ -521,7 +539,7 @@ extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,
521539
int32_t pi32_32kfXtalNPcbParCappF_x100);
522540
/**
523541
* @brief Enables and sets LDO for 16MHz XTAL
524-
* @param none
542+
*
525543
* @return none
526544
*/
527545
extern void POWER_SetXtal16mhzLdo(void);

‎mcux/devices/LPC55S69/fsl_reset.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
#include "fsl_device_registers.h"
1717

1818
/*!
19-
* @addtogroup ksdk_common
19+
* @addtogroup reset
2020
* @{
2121
*/
2222

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