MK64F12: Update device files to SDK 2.8.2

Update MK64F12 to SDK 2.8.2

Origin: MCUXpresso SDK
License: BSD 3-Clause
URL: mcux.nxp.com
Maintained-by: External

Signed-off-by: Mahesh Mahadevan <[email protected]>

Author: mmahadevan108

mcux/devices/MK64F12/MK64F12_features.h

@@ -1,13 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 2.15, 2016-03-21
-**     Build:               b190822
+**     Build:               b200409
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2019 NXP
+**     Copyright 2016-2020 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -390,6 +390,8 @@
 #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
+/* @brief Has Extend MDIO Support. */
+#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (0)
 
 /* EWM module features */
 
@@ -822,6 +824,8 @@
 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0)
 /* @brief Has no QDCTRL. */
 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0)
+/* @brief If instance has only TPM function. */
+#define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0)
 
 /* GPIO module features */
 
@@ -1730,6 +1734,8 @@
 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
 /* @brief Has security violation reset (register bit SRS[SECVIO]). */
 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
+/* @brief Width of SMC registers. */
+#define FSL_FEATURE_SMC_REG_WIDTH (8)
 
 /* DSPI module features */
 

mcux/devices/MK64F12/fsl_clock.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016 - 2019, NXP
+ * Copyright 2016 - 2020, NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -556,7 +556,7 @@ typedef enum _mcg_monitor_mode
     kMCG_MonitorReset /*!< System reset when clock lost.      */
 } mcg_monitor_mode_t;
 
-/*! @brief MCG status. */
+/*! @brief MCG status. Enumeration _mcg_status */
 enum
 {
     kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U),       /*!< Can't switch to target mode. */
@@ -570,7 +570,7 @@ enum
                                                                                it is in use. */
 };
 
-/*! @brief MCG status flags. */
+/*! @brief MCG status flags. Enumeration _mcg_status_flags_t */
 enum
 {
     kMCG_Osc0LostFlag   = (1U << 0U), /*!< OSC0 lost.         */
@@ -580,14 +580,14 @@ enum
     kMCG_Pll0LockFlag   = (1U << 6U), /*!< PLL0 locked.       */
 };
 
-/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
+/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. Enumeration _mcg_irclk_enable_mode */
 enum
 {
     kMCG_IrclkEnable       = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable.              */
     kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
 };
 
-/*! @brief MCG PLL clock enable mode definition. */
+/*! @brief MCG PLL clock enable mode definition. Enumeration _mcg_pll_enable_mode */
 enum
 {
     kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
@@ -616,7 +616,7 @@ typedef enum _mcg_mode
 /*! @brief MCG PLL configuration. */
 typedef struct _mcg_pll_config
 {
-    uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */
+    uint8_t enableMode; /*!< Enable mode. OR'ed value of enumeration _mcg_pll_enable_mode. */
     uint8_t prdiv;      /*!< Reference divider PRDIV.    */
     uint8_t vdiv;       /*!< VCO divider VDIV.           */
 } mcg_pll_config_t;
@@ -885,7 +885,6 @@ void CLOCK_SetSimConfig(sim_clock_config_t const *config);
  * be used before MCG mode change, to make sure system level clocks are in allowed
  * range.
  *
- * @param config Pointer to the configure structure.
  */
 static inline void CLOCK_SetSimSafeDivs(void)
 {
@@ -982,7 +981,7 @@ static inline void CLOCK_SetLowPowerEnable(bool enable)
  * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
  * using the function in these modes it is not allowed.
  *
- * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
+ * @param enableMode MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
  * @param ircs       MCGIRCLK clock source, choose fast or slow.
  * @param fcrdiv     Fast IRC divider setting (\c FCRDIV).
  * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
@@ -1094,7 +1093,7 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
  * @brief Gets the MCG status flags.
  *
  * This function gets the MCG clock status flags. All status flags are
- * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
+ * returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To
  * check a specific flag, compare the return value with the flag.
  *
  * Example:
@@ -1114,15 +1113,15 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
  * }
  * @endcode
  *
- * @return  Logical OR value of the @ref _mcg_status_flags_t.
+ * @return  Logical OR value of the enumeration _mcg_status_flags_t.
  */
 uint32_t CLOCK_GetStatusFlags(void);
 
 /*!
  * @brief Clears the MCG status flags.
  *
  * This function clears the MCG clock lock lost status. The parameter is a logical
- * OR value of the flags to clear. See @ref _mcg_status_flags_t.
+ * OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
  *
  * Example:
  * @code
@@ -1132,7 +1131,7 @@ uint32_t CLOCK_GetStatusFlags(void);
  * @endcode
  *
  * @param mask The status flags to clear. This is a logical OR of members of the
- *             enumeration @ref _mcg_status_flags_t.
+ *             enumeration _mcg_status_flags_t.
  */
 void CLOCK_ClearStatusFlags(uint32_t mask);
 
@@ -1506,7 +1505,7 @@ status_t CLOCK_BootToFeeMode(
  *
  * @param  fcrdiv Fast IRC divider, FCRDIV.
  * @param  ircs   The internal reference clock to select, IRCS.
- * @param  ircEnableMode  The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
+ * @param  ircEnableMode  The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
  *
  * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
  * @retval kStatus_Success Switched to the target mode successfully.
@@ -1549,7 +1548,7 @@ status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mc
  * chooses the correct path.
  *
  * @param  config Pointer to the target MCG mode configuration structure.
- * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
+ * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
  *
  * @note If the external clock is used in the target mode, ensure that it is
  * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this