added i2s tx

Author: pyamnihc

i2s_tx.v

@@ -0,0 +1,34 @@
+module i2s_tx #(
+        parameter AUDIO_DW = 8
+        ) (
+	input sck_i,
+	input ws_i,
+        output sd_o,
+	input [AUDIO_DW-1:0] l_data_i,
+	input [AUDIO_DW-1:0] r_data_i,
+        output l_load_en_o,
+        output r_load_en_o
+);
+    reg wsd[1:0];
+    always @(posedge sck_i) begin
+        wsd[0] <= ws_i;
+        wsd[1] <= wsd[0];
+    end
+    assign l_load_en_o = wsd[0] & !ws_i;
+    assign r_load_en_o = !wsd[0] & ws_i;
+    
+    wire wsp;
+    assign wsp = wsd[0] ^ wsd[1];
+
+    reg [AUDIO_DW-1:0] sd_shift_reg;
+    wire [AUDIO_DW-1:0] l_data, r_data;
+    assign l_data = !wsd[0] ? l_data_i : {AUDIO_DW{1'b0}};
+    assign r_data = wsd[0] ? r_data_i : {AUDIO_DW{1'b0}};
+
+    always @(negedge sck_i) begin
+        if (wsp == 1) sd_shift_reg <= l_data | r_data;
+        else sd_shift_reg <= {sd_shift_reg[AUDIO_DW-2:0], 1'b0};
+    end
+    assign sd_o = sd_shift_reg[AUDIO_DW-1];
+
+endmodule

info.yaml

@@ -10,6 +10,7 @@ project:
     - spi_slave_mem_interface.v
     - register_map.v
     - prbs15.v
+    - i2s_tx.v
   top_module:  "tt_um_spi_register_map"      # put the name of your top module here, make it unique by prepending your github username
 
 # How many tiles your design occupies? A single tile is about 167x108 uM.

src/Makefile

@@ -9,7 +9,7 @@ TOPLEVEL_LANG ?= verilog
 ifneq ($(GATES),yes)
 
 # this is the only part you should need to modify:
-VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_spi_register_map.v $(PWD)/spi_slave_mem_interface.v $(PWD)/register_map.v $(PWD)/prbs15.v
+VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_spi_register_map.v $(PWD)/spi_slave_mem_interface.v $(PWD)/register_map.v $(PWD)/prbs15.v $(PWD)/i2s_tx.v
 
 else
 

src/i2s_tx.v

@@ -0,0 +1,34 @@
+module i2s_tx #(
+        parameter AUDIO_DW = 8
+        ) (
+	input sck_i,
+	input ws_i,
+        output sd_o,
+	input [AUDIO_DW-1:0] l_data_i,
+	input [AUDIO_DW-1:0] r_data_i,
+        output l_load_en_o,
+        output r_load_en_o
+);
+    reg wsd[1:0];
+    always @(posedge sck_i) begin
+        wsd[0] <= ws_i;
+        wsd[1] <= wsd[0];
+    end
+    assign l_load_en_o = wsd[0] & !ws_i;
+    assign r_load_en_o = !wsd[0] & ws_i;
+    
+    wire wsp;
+    assign wsp = wsd[0] ^ wsd[1];
+
+    reg [AUDIO_DW-1:0] sd_shift_reg;
+    wire [AUDIO_DW-1:0] l_data, r_data;
+    assign l_data = !wsd[0] ? l_data_i : {AUDIO_DW{1'b0}};
+    assign r_data = wsd[0] ? r_data_i : {AUDIO_DW{1'b0}};
+
+    always @(negedge sck_i) begin
+        if (wsp == 1) sd_shift_reg <= l_data | r_data;
+        else sd_shift_reg <= {sd_shift_reg[AUDIO_DW-2:0], 1'b0};
+    end
+    assign sd_o = sd_shift_reg[AUDIO_DW-1];
+
+endmodule

src/tb.v

@@ -21,6 +21,11 @@ module tb();
     localparam MAX_CLOCKS = 1048576;
     localparam TEST_COUNT = 8;
 
+    localparam SCK_PERIOD = 62500/4;
+    localparam WS_PERIOD = 2*AUDIO_DW*SCK_PERIOD;
+    localparam MAX_SAMPLES = 32;
+    localparam AUDIO_DW = 8;
+    
     reg clk, rst_n;
     reg [DATA_WIDTH-1:0] rand_addr_arr [TEST_COUNT-1:0];
     reg [DATA_WIDTH-1:0] rand_val_arr [NUM_CONFIG_REG+NUM_STATUS_REG-1:0];
@@ -29,15 +34,14 @@ module tb();
     integer count_i;
     reg fail_flag;
 
-    assign uio_in[5] = 0;
-    assign uio_in[4] = 1;
-    
     reg finish;
 
     initial begin
         finish = 0;
         clk = 0;
         rst_n = 1;
+        sck = 0;
+        ws = 0;
         #(10*CLK_PERIOD)    init_design();
                             init_spi();
                             prbs_init();
@@ -50,16 +54,57 @@ module tb();
         // #(10*CLK_PERIOD)    $finish;
     end
 
+    reg [AUDIO_DW-1:0] sd_buffer, recv_l_data, recv_r_data;
+    initial begin 
+        sd_buffer = 0;
+    end
+    always @(posedge sck) begin
+        sd_buffer <= {sd_buffer[AUDIO_DW-2:0], sd};
+    end
+    
+    reg wsd[1:0];
+    always @(posedge sck) begin
+        wsd[0] <= ws;
+        wsd[1] <= wsd[0];
+    end
+    
+    wire wsp;
+    assign wsp = wsd[0] ^ wsd[1];
+
+    reg [31:0] sample_count;
+    initial begin
+        sample_count = 0;
+    end
+    always @(negedge sck) begin
+        if (wsp == 1'b1) begin
+            sample_count <= sample_count + 1;
+            if (ws == 1'b1) begin
+                recv_l_data <= sd_buffer;
+                $display("recv: 0x%0h", recv_l_data);
+
+            end else if (ws == 1'b0) begin
+                recv_r_data <= sd_buffer;
+                $display("recv: 0x%0h", recv_r_data);
+            end
+        end else if (sample_count >= MAX_SAMPLES) finish = 1;
+    end
+
+
     reg [63:0] clk_count;
     initial clk_count = 0;
     always @(posedge clk) begin
         clk_count <= clk_count + 1;
     end
 
     always #(CLK_PERIOD/2) clk = !clk;
+    always #(SCK_PERIOD/2) sck = !sck;
+    always #(WS_PERIOD/2) ws = !ws;
 
     reg sck_i, cs_ni;
     wire sdi_i, sdo_o;
+    reg sck;
+    reg ws;
+    wire sd;
 
     // wire up the inputs and outputs
     // reg  clk;
@@ -98,6 +143,9 @@ module tb();
     assign uio_in[1] = sdi_i;
     assign sdo_o = uio_out[2];
     assign uio_in[3] = cs_ni;
+    assign uio_in[4] = sck;
+    assign uio_in[5] = ws;
+    assign sd = uio_out[6];
 
     assign uio_oe = 8'b1100_0100;
 

src/tt_um_spi_register_map.v

@@ -46,9 +46,8 @@ module tt_um_spi_register_map (
     endgenerate
 
     assign uio_out[7] = ^prbs_frame;
-    assign uio_out[6] = |config_bus_o;
-    assign status_bus_i[DATA_WIDTH*(NUM_STATUS_REG/2)-1:0] = {(DATA_WIDTH*(NUM_STATUS_REG/2)){uio_in[5]}};
-    assign status_bus_i[DATA_WIDTH*NUM_STATUS_REG-1:DATA_WIDTH*(NUM_STATUS_REG/2)] = {(DATA_WIDTH*(NUM_STATUS_REG/2)){uio_in[4]}};
+    assign status_bus_i[DATA_WIDTH*(NUM_STATUS_REG/2)-1:0] = {(DATA_WIDTH*(NUM_STATUS_REG/2)){1'b0}};
+    assign status_bus_i[DATA_WIDTH*NUM_STATUS_REG-1:DATA_WIDTH*(NUM_STATUS_REG/2)] = {(DATA_WIDTH*(NUM_STATUS_REG/2)){1'b1}};
 
     wire [ADDR_WIDTH-1:0] spi_addr;
     wire [DATA_WIDTH-1:0] spi_write_data, spi_read_data;
@@ -103,4 +102,49 @@ module tt_um_spi_register_map (
         .prbs_frame_o(prbs_frame)
     );
 
+    localparam AUDIO_DW = 8;
+
+    wire sck;
+    assign sck = uio_in[4];
+    wire ws;
+    assign ws = uio_in[5];
+    wire sd;
+    assign uio_out[6] = sd;
+
+    reg [AUDIO_DW-1:0] l_data, r_data; 
+    wire l_load_en, r_load_en;
+    
+    reg l_load_reg [1:0];
+    reg r_load_reg [1:0];
+    always @(posedge clk) begin
+        if (!rst_n) begin
+            l_load_reg[0] <= 'b0; l_load_reg[1] = 'b0;
+            r_load_reg[0] <= 'b0; r_load_reg[1] = 'b0;
+        end else begin
+            l_load_reg[0] <= l_load_en; l_load_reg[1] <= l_load_reg[0];
+            r_load_reg[0] <= r_load_en; r_load_reg[1] <= r_load_reg[0];
+        end
+    end
+    wire l_load_pulse;
+    assign l_load_pulse = l_load_reg[0] && !l_load_reg[1];
+    wire r_load_pulse;
+    assign r_load_pulse = r_load_reg[0] && !r_load_reg[1];
+
+    always @(posedge clk) begin
+        if (l_load_pulse) l_data <= prbs_frame;
+        if (r_load_pulse) r_data <= prbs_frame;
+    end
+
+    i2s_tx #(
+        .AUDIO_DW(AUDIO_DW)
+        ) UUT_i2s_tx (
+        .sck_i(sck),
+        .ws_i(ws),
+        .sd_o(sd),
+        .l_data_i(l_data),
+        .r_data_i(r_data),
+        .l_load_en_o(l_load_en),
+        .r_load_en_o(r_load_en)
+    );
+
 endmodule