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It seems, that pymodbus 3.9.0 misinterprets the on-wire protocol.
According to the Modbus Application Protocol 1.1b document, section 6.1, the data bytes should be interpreted one by one starting with the first byte and the bits should be interpreted starting at the LSB for each byte.
In my case, the device returns 2 data bytes: 0xf5, 0xff and so the bits should be interpreted as follows:
starting with the first byte (0xf5), interpreting the bits starting at LSB: true, false, true, false, true, true, true, true
then the 2nd byte (0xff), starting at LSB: true, true, ...
The modbus dissector in wireshark confirms it:
It looks like that commit d47dc65 has broken the bit order in 3.9.0.
The text was updated successfully, but these errors were encountered:
My modbus device is reporting the following coils starting at address 0x100: true, false, true, false, true, true, ... .
pymodbus 3.8.6 returned the bits in the correct order:
pymodbus 3.9.0 returns the values byte-wise swapped:
It seems, that pymodbus 3.9.0 misinterprets the on-wire protocol.
According to the Modbus Application Protocol 1.1b document, section 6.1, the data bytes should be interpreted one by one starting with the first byte and the bits should be interpreted starting at the LSB for each byte.
In my case, the device returns 2 data bytes: 0xf5, 0xff and so the bits should be interpreted as follows:
The modbus dissector in wireshark confirms it:
It looks like that commit d47dc65 has broken the bit order in 3.9.0.
The text was updated successfully, but these errors were encountered: