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import org .quisl .framework .java .registers .common .RegisterUnitPrefixes ;
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import org .quisl .framework .java .units .computing .classical .binary .deterministic .bits .Bit ;
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- import java .util .ArrayList ;
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- import java .util .List ;
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+ import java .util .Map ;
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import java .util .Objects ;
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+ import java .util .concurrent .ConcurrentHashMap ;
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public class ClassicalRegister extends Register {
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- private List < Bit > bits ;
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+ private Map < Long , Bit > bits ;
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public ClassicalRegister (Long id , Integer numBits ) {
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super ( id , RegisterUnitPrefixes .CLASSICAL_REGISTER_UNIT .getRegisterUnitCharacter (),
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( "cl-reg-" + id ), numBits );
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- this .bits = new ArrayList <>(numBits );
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+ this .bits = new ConcurrentHashMap <>(numBits );
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this .addBits (numBits );
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@@ -29,7 +29,7 @@ public ClassicalRegister(Long id, String classicalRegisterName, Integer numBits)
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super ( id , RegisterUnitPrefixes .CLASSICAL_REGISTER_UNIT .getRegisterUnitCharacter (),
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classicalRegisterName , numBits );
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- this .bits = new ArrayList <>(numBits );
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+ this .bits = new ConcurrentHashMap <>(numBits );
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this .addBits (numBits );
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@@ -41,19 +41,19 @@ public void addBits(Integer numBits) {
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Bit bit = new Bit (currentBit );
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- this .bits .add ( bit );
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+ this .bits .put ( bit . getId (), bit );
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}
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}
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- public List < Bit > getBits () {
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+ public Map < Long , Bit > getBits () {
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return this .bits ;
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}
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- public void setBits (List < Bit > bits ) {
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+ public void setBits (Map < Long , Bit > bits ) {
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this .bits = bits ;
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