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Commit 59ee2c5

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Farhana Aleen
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[AMDGPU] Removed the unnecessary operand size-check-assert from processBaseWithConstOffset().
Summary: 32bit operand sizes are guaranteed by the opcode check AMDGPU::V_ADD_I32_e64 and AMDGPU::V_ADDC_U32_e64. Therefore, we don't any additional operand size-check-assert. Author: FarhanaAleen llvm-svn: 349529
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2 files changed

+36
-2
lines changed

2 files changed

+36
-2
lines changed

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

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@@ -1249,8 +1249,6 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
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if (!Src1->isImm())
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return;
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assert(isInt<32>(*Offset0P) && isInt<32>(Src1->getImm())
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&& "Expected 32bit immediate!!!");
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uint64_t Offset1 = Src1->getImm();
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BaseHi = *Src0;
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llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir

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Original file line numberDiff line numberDiff line change
@@ -152,3 +152,39 @@ body: |
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%44:vreg_64 = REG_SEQUENCE %40, %subreg.sub0, %42, %subreg.sub1
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%45:vreg_64 = GLOBAL_LOAD_DWORDX2 %44, 0, 0, 0, implicit $exec
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...
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---
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# Tests for a successful compilation.
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name: assert_hit
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body: |
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bb.0.entry:
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0
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%3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
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%4:sreg_32_xm0 = COPY $sgpr101
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%5:sreg_32_xm0 = S_MOV_B32 0
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$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
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$sgpr4 = COPY %4
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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%6:vreg_64 = COPY $vgpr0_vgpr1
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%7:vgpr_32 = V_AND_B32_e32 255, %6.sub0, implicit $exec
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%8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%9:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, %8, %subreg.sub1
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%10:vgpr_32 = V_LSHLREV_B32_e64 7, %6.sub0, implicit $exec
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%11:vgpr_32 = V_AND_B32_e32 -32768, killed %10, implicit $exec
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%12:sgpr_32 = COPY %1.sub1
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%13:vgpr_32 = COPY %5
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%14:vgpr_32, %15:sreg_64_xexec = V_ADD_I32_e64 %1.sub0, %11, implicit $exec
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%16:vgpr_32 = COPY %12
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%17:vgpr_32, dead %18:sreg_64_xexec = V_ADDC_U32_e64 %16, %13, killed %15, implicit $exec
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%19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1
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%20:vreg_64 = V_LSHLREV_B64 3, %9, implicit $exec
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%21:vgpr_32, %22:sreg_64_xexec = V_ADD_I32_e64 %14, %20.sub0, implicit $exec
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%23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, implicit $exec
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%25:sgpr_32 = S_MOV_B32 6144
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%26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %21, %25, implicit $exec
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%28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 4294967295, killed %27, implicit $exec
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%30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
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%31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, implicit $exec
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...

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