@@ -606,7 +606,7 @@ struct AigerWriter
606
606
f << stringf (" c\n Generated by %s\n " , yosys_version_str);
607
607
}
608
608
609
- void write_map (std::ostream &f, bool verbose_map)
609
+ void write_map (std::ostream &f, bool verbose_map, bool no_startoffset )
610
610
{
611
611
dict<int , string> input_lines;
612
612
dict<int , string> init_lines;
@@ -627,32 +627,33 @@ struct AigerWriter
627
627
continue ;
628
628
629
629
int a = aig_map.at (sig[i]);
630
+ int index = no_startoffset ? i : (wire->start_offset +i);
630
631
631
632
if (verbose_map)
632
- wire_lines[a] += stringf (" wire %d %d %s\n " , a, wire-> start_offset +i , log_id (wire));
633
+ wire_lines[a] += stringf (" wire %d %d %s\n " , a, index , log_id (wire));
633
634
634
635
if (wire->port_input ) {
635
636
log_assert ((a & 1 ) == 0 );
636
- input_lines[a] += stringf (" input %d %d %s\n " , (a >> 1 )-1 , wire-> start_offset +i , log_id (wire));
637
+ input_lines[a] += stringf (" input %d %d %s\n " , (a >> 1 )-1 , index , log_id (wire));
637
638
}
638
639
639
640
if (wire->port_output ) {
640
641
int o = ordered_outputs.at (sig[i]);
641
- output_lines[o] += stringf (" output %d %d %s\n " , o, wire-> start_offset +i , log_id (wire));
642
+ output_lines[o] += stringf (" output %d %d %s\n " , o, index , log_id (wire));
642
643
}
643
644
644
645
if (init_inputs.count (sig[i])) {
645
646
int a = init_inputs.at (sig[i]);
646
647
log_assert ((a & 1 ) == 0 );
647
- init_lines[a] += stringf (" init %d %d %s\n " , (a >> 1 )-1 , wire-> start_offset +i , log_id (wire));
648
+ init_lines[a] += stringf (" init %d %d %s\n " , (a >> 1 )-1 , index , log_id (wire));
648
649
}
649
650
650
651
if (ordered_latches.count (sig[i])) {
651
652
int l = ordered_latches.at (sig[i]);
652
653
if (zinit_mode && (aig_latchinit.at (l) == 1 ))
653
- latch_lines[l] += stringf (" invlatch %d %d %s\n " , l, wire-> start_offset +i , log_id (wire));
654
+ latch_lines[l] += stringf (" invlatch %d %d %s\n " , l, index , log_id (wire));
654
655
else
655
- latch_lines[l] += stringf (" latch %d %d %s\n " , l, wire-> start_offset +i , log_id (wire));
656
+ latch_lines[l] += stringf (" latch %d %d %s\n " , l, index , log_id (wire));
656
657
}
657
658
}
658
659
}
@@ -713,6 +714,9 @@ struct AigerBackend : public Backend {
713
714
log (" -vmap <filename>\n " );
714
715
log (" like -map, but more verbose\n " );
715
716
log (" \n " );
717
+ log (" -no-startoffset\n " );
718
+ log (" make indexes zero based, enable using map files with smt solvers.\n " );
719
+ log (" \n " );
716
720
log (" -I, -O, -B, -L\n " );
717
721
log (" If the design contains no input/output/assert/flip-flop then create one\n " );
718
722
log (" dummy input/output/bad_state-pin or latch to make the tools reading the\n " );
@@ -730,6 +734,7 @@ struct AigerBackend : public Backend {
730
734
bool omode = false ;
731
735
bool bmode = false ;
732
736
bool lmode = false ;
737
+ bool no_startoffset = false ;
733
738
std::string map_filename;
734
739
735
740
log_header (design, " Executing AIGER backend.\n " );
@@ -762,6 +767,10 @@ struct AigerBackend : public Backend {
762
767
verbose_map = true ;
763
768
continue ;
764
769
}
770
+ if (args[argidx] == " -no-startoffset" ) {
771
+ no_startoffset = true ;
772
+ continue ;
773
+ }
765
774
if (args[argidx] == " -I" ) {
766
775
imode = true ;
767
776
continue ;
@@ -804,7 +813,7 @@ struct AigerBackend : public Backend {
804
813
mapf.open (map_filename.c_str (), std::ofstream::trunc);
805
814
if (mapf.fail ())
806
815
log_error (" Can't open file `%s' for writing: %s\n " , map_filename.c_str (), strerror (errno));
807
- writer.write_map (mapf, verbose_map);
816
+ writer.write_map (mapf, verbose_map, no_startoffset );
808
817
}
809
818
}
810
819
} AigerBackend;
0 commit comments