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Blackbox all whiteboxes after synthesis
This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <[email protected]>
1 parent c8b45a4 commit cae905f

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16 files changed

+24
-9
lines changed

16 files changed

+24
-9
lines changed

‎techlibs/achronix/synth_achronix.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -173,6 +173,7 @@ struct SynthAchronixPass : public ScriptPass {
173173
run("hierarchy -check");
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run("stat");
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run("check -noinit");
176+
run("blackbox =A:whitebox");
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}
177178

178179
if (check_label("vout"))

‎techlibs/anlogic/synth_anlogic.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,7 @@ struct SynthAnlogicPass : public ScriptPass
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
214+
run("blackbox =A:whitebox");
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}
215216

216217
if (check_label("edif"))

‎techlibs/coolrunner2/synth_coolrunner2.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -192,6 +192,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
195+
run("blackbox =A:whitebox");
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}
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197198
if (check_label("json"))

‎techlibs/easic/synth_easic.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -175,6 +175,7 @@ struct SynthEasicPass : public ScriptPass
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
178+
run("blackbox =A:whitebox");
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}
179180

180181
if (check_label("vlog"))

‎techlibs/ecp5/synth_ecp5.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -385,6 +385,7 @@ struct SynthEcp5Pass : public ScriptPass
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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run("blackbox =A:whitebox");
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}
389390

390391
if (check_label("blif"))

‎techlibs/efinix/synth_efinix.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,7 @@ struct SynthEfinixPass : public ScriptPass
213213
run("hierarchy -check");
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run("stat");
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run("check -noinit");
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run("blackbox =A:whitebox");
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}
217218

218219
if (check_label("edif"))

‎techlibs/gowin/synth_gowin.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -289,6 +289,7 @@ struct SynthGowinPass : public ScriptPass
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
292+
run("blackbox =A:whitebox");
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}
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294295
if (check_label("vout"))

‎techlibs/greenpak4/synth_greenpak4.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
196196
run("hierarchy -check");
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run("stat");
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run("check -noinit");
199+
run("blackbox =A:whitebox");
199200
}
200201

201202
if (check_label("json"))

‎techlibs/ice40/synth_ice40.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -417,6 +417,7 @@ struct SynthIce40Pass : public ScriptPass
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
420+
run("blackbox =A:whitebox");
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}
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422423
if (check_label("blif"))

‎techlibs/intel/synth_intel.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -233,6 +233,7 @@ struct SynthIntelPass : public ScriptPass {
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run("hierarchy -check");
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run("stat");
235235
run("check -noinit");
236+
run("blackbox =A:whitebox");
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}
237238

238239
if (check_label("vqm")) {

‎techlibs/intel_alm/synth_intel_alm.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -274,6 +274,7 @@ struct SynthIntelALMPass : public ScriptPass {
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run("hierarchy -check");
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run("stat");
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run("check");
277+
run("blackbox =A:whitebox");
277278
}
278279

279280
if (check_label("quartus")) {

‎techlibs/machxo2/synth_machxo2.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,7 @@ struct SynthMachXO2Pass : public ScriptPass
212212
{
213213
run("hierarchy -check");
214214
run("stat");
215+
run("blackbox =A:whitebox");
215216
}
216217

217218
if (check_label("blif"))

‎techlibs/nexus/synth_nexus.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -406,6 +406,7 @@ struct SynthNexusPass : public ScriptPass
406406
run("hierarchy -check");
407407
run("stat");
408408
run("check -noinit");
409+
run("blackbox =A:whitebox");
409410
}
410411

411412
if (check_label("json"))

‎techlibs/sf2/synth_sf2.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -228,6 +228,7 @@ struct SynthSf2Pass : public ScriptPass
228228
run("hierarchy -check");
229229
run("stat");
230230
run("check -noinit");
231+
run("blackbox =A:whitebox");
231232
}
232233

233234
if (check_label("edif"))

‎techlibs/xilinx/synth_xilinx.cc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -662,6 +662,7 @@ struct SynthXilinxPass : public ScriptPass
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run("hierarchy -check");
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run("stat -tech xilinx");
664664
run("check -noinit");
665+
run("blackbox =A:whitebox");
665666
}
666667

667668
if (check_label("edif")) {

‎tests/arch/ecp5/mux.ys

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -15,9 +15,9 @@ proc
1515
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
1616
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
1717
cd mux4 # Constrain all select calls below inside the top module
18-
select -assert-count 1 t:L6MUX21
19-
select -assert-count 4 t:LUT4
20-
select -assert-count 2 t:PFUMX
18+
select -assert-max 1 t:L6MUX21
19+
select -assert-max 4 t:LUT4
20+
select -assert-max 2 t:PFUMX
2121

2222
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
2323

@@ -27,9 +27,9 @@ proc
2727
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
2828
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
2929
cd mux8 # Constrain all select calls below inside the top module
30-
select -assert-count 1 t:L6MUX21
31-
select -assert-count 7 t:LUT4
32-
select -assert-count 2 t:PFUMX
30+
select -assert-max 1 t:L6MUX21
31+
select -assert-max 7 t:LUT4
32+
select -assert-max 2 t:PFUMX
3333

3434
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
3535

@@ -39,8 +39,8 @@ proc
3939
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
4040
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
4141
cd mux16 # Constrain all select calls below inside the top module
42-
select -assert-count 8 t:L6MUX21
43-
select -assert-count 26 t:LUT4
44-
select -assert-count 12 t:PFUMX
42+
select -assert-max 12 t:L6MUX21
43+
select -assert-max 34 t:LUT4
44+
select -assert-max 17 t:PFUMX
4545

4646
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D

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