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ARM: dts: uniphier: sync Device Trees with upstream Linux
I periodically sync Device Trees for better maintainability. Signed-off-by: Masahiro Yamada <[email protected]>
1 parent aac641b commit c4adc50

22 files changed

+99
-138
lines changed

‎arch/arm/dts/uniphier-common32.dtsi

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#size-cells = <1>;
2323
ranges;
2424
interrupt-parent = <&intc>;
25+
u-boot,dm-pre-reloc;
2526

2627
serial0: serial@54006800 {
2728
compatible = "socionext,uniphier-uart";
@@ -65,9 +66,12 @@
6566

6667
system_bus: system-bus@58c00000 {
6768
compatible = "socionext,uniphier-system-bus";
69+
status = "disabled";
6870
reg = <0x58c00000 0x400>;
6971
#address-cells = <2>;
7072
#size-cells = <1>;
73+
pinctrl-names = "default";
74+
pinctrl-0 = <&pinctrl_system_bus>;
7175
};
7276

7377
smpctrl@59800000 {
@@ -109,9 +113,15 @@
109113
interrupt-controller;
110114
};
111115

112-
pinctrl: pinctrl@5f801000 {
113-
/* specify compatible in each SoC DTSI */
114-
reg = <0x5f801000 0xe00>;
116+
soc-glue@5f800000 {
117+
compatible = "simple-mfd", "syscon";
118+
reg = <0x5f800000 0x2000>;
119+
u-boot,dm-pre-reloc;
120+
121+
pinctrl: pinctrl {
122+
/* specify compatible in each SoC DTSI */
123+
u-boot,dm-pre-reloc;
124+
};
115125
};
116126

117127
sysctrl: sysctrl@61840000 {
@@ -124,8 +134,12 @@
124134

125135
nand: nand@68000000 {
126136
compatible = "denali,denali-nand-dt";
127-
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
137+
status = "disabled";
128138
reg-names = "nand_data", "denali_reg";
139+
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
140+
interrupts = <0 65 4>;
141+
pinctrl-names = "default";
142+
pinctrl-0 = <&pinctrl_nand>;
129143
};
130144
};
131145
};

‎arch/arm/dts/uniphier-ph1-ld11-ref.dts

Lines changed: 2 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
/*
22
* Device Tree Source for UniPhier PH1-LD11 Reference Board
33
*
4-
* Copyright (C) 2016 Masahiro Yamada <[email protected]>
4+
* Copyright (C) 2016 Socionext Inc.
5+
* Author: Masahiro Yamada <[email protected]>
56
*
67
* SPDX-License-Identifier: GPL-2.0+ X11
78
*/
@@ -62,20 +63,10 @@
6263
};
6364

6465
/* for U-Boot only */
65-
/ {
66-
soc {
67-
u-boot,dm-pre-reloc;
68-
};
69-
};
70-
7166
&serial0 {
7267
u-boot,dm-pre-reloc;
7368
};
7469

75-
&pinctrl {
76-
u-boot,dm-pre-reloc;
77-
};
78-
7970
&pinctrl_uart0 {
8071
u-boot,dm-pre-reloc;
8172
};

‎arch/arm/dts/uniphier-ph1-ld11.dtsi

Lines changed: 37 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,14 @@
11
/*
22
* Device Tree Source for UniPhier PH1-LD11 SoC
33
*
4-
* Copyright (C) 2016 Masahiro Yamada <[email protected]>
4+
* Copyright (C) 2016 Socionext Inc.
5+
* Author: Masahiro Yamada <[email protected]>
56
*
67
* SPDX-License-Identifier: GPL-2.0+ X11
78
*/
89

10+
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
11+
912
/ {
1013
compatible = "socionext,ph1-ld11";
1114
#address-cells = <2>;
@@ -16,24 +19,41 @@
1619
#address-cells = <2>;
1720
#size-cells = <0>;
1821

19-
cpu@0 {
22+
cpu-map {
23+
cluster0 {
24+
core0 {
25+
cpu = <&cpu0>;
26+
};
27+
core1 {
28+
cpu = <&cpu1>;
29+
};
30+
};
31+
};
32+
33+
cpu0: cpu@0 {
2034
device_type = "cpu";
2135
compatible = "arm,cortex-a53", "arm,armv8";
2236
reg = <0 0x000>;
2337
enable-method = "spin-table";
24-
cpu-release-addr = <0 0x80000100>;
38+
cpu-release-addr = <0 0x80000000>;
2539
};
2640

27-
cpu@1 {
41+
cpu1: cpu@1 {
2842
device_type = "cpu";
2943
compatible = "arm,cortex-a53", "arm,armv8";
3044
reg = <0 0x001>;
3145
enable-method = "spin-table";
32-
cpu-release-addr = <0 0x80000100>;
46+
cpu-release-addr = <0 0x80000000>;
3347
};
3448
};
3549

3650
clocks {
51+
refclk: ref {
52+
compatible = "fixed-clock";
53+
#clock-cells = <0>;
54+
clock-frequency = <25000000>;
55+
};
56+
3757
uart_clk: uart_clk {
3858
#clock-cells = <0>;
3959
compatible = "fixed-clock";
@@ -60,6 +80,7 @@
6080
#address-cells = <1>;
6181
#size-cells = <1>;
6282
ranges = <0 0 0 0xffffffff>;
83+
u-boot,dm-pre-reloc;
6384

6485
serial0: serial@54006800 {
6586
compatible = "socionext,uniphier-uart";
@@ -183,6 +204,8 @@
183204
reg = <0x58c00000 0x400>;
184205
#address-cells = <2>;
185206
#size-cells = <1>;
207+
pinctrl-names = "default";
208+
pinctrl-0 = <&pinctrl_system_bus>;
186209
};
187210

188211
smpctrl@59800000 {
@@ -226,9 +249,15 @@
226249
#clock-cells = <1>;
227250
};
228251

229-
pinctrl: pinctrl@5f801000 {
230-
compatible = "socionext,ph1-ld11-pinctrl", "syscon";
231-
reg = <0x5f801000 0xe00>;
252+
soc-glue@5f800000 {
253+
compatible = "simple-mfd", "syscon";
254+
reg = <0x5f800000 0x2000>;
255+
u-boot,dm-pre-reloc;
256+
257+
pinctrl: pinctrl {
258+
compatible = "socionext,uniphier-ld11-pinctrl";
259+
u-boot,dm-pre-reloc;
260+
};
232261
};
233262

234263
gic: interrupt-controller@5fe00000 {

‎arch/arm/dts/uniphier-ph1-ld20-ref.dts

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -51,20 +51,10 @@
5151
};
5252

5353
/* for U-Boot only */
54-
/ {
55-
soc {
56-
u-boot,dm-pre-reloc;
57-
};
58-
};
59-
6054
&serial0 {
6155
u-boot,dm-pre-reloc;
6256
};
6357

64-
&pinctrl {
65-
u-boot,dm-pre-reloc;
66-
};
67-
6858
&pinctrl_uart0 {
6959
u-boot,dm-pre-reloc;
7060
};

‎arch/arm/dts/uniphier-ph1-ld20.dtsi

Lines changed: 24 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,8 @@
66
* SPDX-License-Identifier: GPL-2.0+ X11
77
*/
88

9+
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
10+
911
/ {
1012
compatible = "socionext,ph1-ld20";
1113
#address-cells = <2>;
@@ -41,35 +43,41 @@
4143
compatible = "arm,cortex-a72", "arm,armv8";
4244
reg = <0 0x000>;
4345
enable-method = "spin-table";
44-
cpu-release-addr = <0 0x80000100>;
46+
cpu-release-addr = <0 0x80000000>;
4547
};
4648

4749
cpu1: cpu@1 {
4850
device_type = "cpu";
4951
compatible = "arm,cortex-a72", "arm,armv8";
5052
reg = <0 0x001>;
5153
enable-method = "spin-table";
52-
cpu-release-addr = <0 0x80000100>;
54+
cpu-release-addr = <0 0x80000000>;
5355
};
5456

5557
cpu2: cpu@100 {
5658
device_type = "cpu";
5759
compatible = "arm,cortex-a53", "arm,armv8";
5860
reg = <0 0x100>;
5961
enable-method = "spin-table";
60-
cpu-release-addr = <0 0x80000100>;
62+
cpu-release-addr = <0 0x80000000>;
6163
};
6264

6365
cpu3: cpu@101 {
6466
device_type = "cpu";
6567
compatible = "arm,cortex-a53", "arm,armv8";
6668
reg = <0 0x101>;
6769
enable-method = "spin-table";
68-
cpu-release-addr = <0 0x80000100>;
70+
cpu-release-addr = <0 0x80000000>;
6971
};
7072
};
7173

7274
clocks {
75+
refclk: ref {
76+
compatible = "fixed-clock";
77+
#clock-cells = <0>;
78+
clock-frequency = <25000000>;
79+
};
80+
7381
uart_clk: uart_clk {
7482
#clock-cells = <0>;
7583
compatible = "fixed-clock";
@@ -96,6 +104,7 @@
96104
#address-cells = <1>;
97105
#size-cells = <1>;
98106
ranges = <0 0 0 0xffffffff>;
107+
u-boot,dm-pre-reloc;
99108

100109
serial0: serial@54006800 {
101110
compatible = "socionext,uniphier-uart";
@@ -219,6 +228,8 @@
219228
reg = <0x58c00000 0x400>;
220229
#address-cells = <2>;
221230
#size-cells = <1>;
231+
pinctrl-names = "default";
232+
pinctrl-0 = <&pinctrl_system_bus>;
222233
};
223234

224235
smpctrl@59800000 {
@@ -243,9 +254,15 @@
243254
bus-width = <4>;
244255
};
245256

246-
pinctrl: pinctrl@5f801000 {
247-
compatible = "socionext,ph1-ld20-pinctrl", "syscon";
248-
reg = <0x5f801000 0xe00>;
257+
soc-glue@5f800000 {
258+
compatible = "simple-mfd", "syscon";
259+
reg = <0x5f800000 0x2000>;
260+
u-boot,dm-pre-reloc;
261+
262+
pinctrl: pinctrl {
263+
compatible = "socionext,uniphier-ld20-pinctrl";
264+
u-boot,dm-pre-reloc;
265+
};
249266
};
250267

251268
gic: interrupt-controller@5fe00000 {

‎arch/arm/dts/uniphier-ph1-ld4-ref.dts

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -69,20 +69,10 @@
6969
};
7070

7171
/* for U-Boot only */
72-
/ {
73-
soc {
74-
u-boot,dm-pre-reloc;
75-
};
76-
};
77-
7872
&serial0 {
7973
u-boot,dm-pre-reloc;
8074
};
8175

82-
&pinctrl {
83-
u-boot,dm-pre-reloc;
84-
};
85-
8676
&pinctrl_uart0 {
8777
u-boot,dm-pre-reloc;
8878
};

‎arch/arm/dts/uniphier-ph1-ld4.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -310,7 +310,7 @@
310310
};
311311

312312
&pinctrl {
313-
compatible = "socionext,ph1-ld4-pinctrl", "syscon";
313+
compatible = "socionext,uniphier-ld4-pinctrl";
314314
};
315315

316316
&sysctrl {

‎arch/arm/dts/uniphier-ph1-ld6b-ref.dts

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -71,20 +71,10 @@
7171
};
7272

7373
/* for U-Boot only */
74-
/ {
75-
soc {
76-
u-boot,dm-pre-reloc;
77-
};
78-
};
79-
8074
&serial0 {
8175
u-boot,dm-pre-reloc;
8276
};
8377

84-
&pinctrl {
85-
u-boot,dm-pre-reloc;
86-
};
87-
8878
&pinctrl_uart0 {
8979
u-boot,dm-pre-reloc;
9080
};

‎arch/arm/dts/uniphier-ph1-ld6b.dtsi

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
compatible = "socionext,ph1-ld6b";
1818
};
1919

20-
/* UART3 unavilable: the pads are not wired to the package balls */
20+
/* UART3 unavailable: the pads are not wired to the package balls */
2121
&serial3 {
2222
status = "disabled";
2323
};
@@ -27,5 +27,5 @@
2727
* which makes the pinctrl driver unshareable.
2828
*/
2929
&pinctrl {
30-
compatible = "socionext,ph1-ld6b-pinctrl", "syscon";
30+
compatible = "socionext,uniphier-ld6b-pinctrl";
3131
};

‎arch/arm/dts/uniphier-ph1-pro4-ace.dts

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -90,20 +90,10 @@
9090
};
9191

9292
/* for U-Boot only */
93-
/ {
94-
soc {
95-
u-boot,dm-pre-reloc;
96-
};
97-
};
98-
9993
&serial0 {
10094
u-boot,dm-pre-reloc;
10195
};
10296

103-
&pinctrl {
104-
u-boot,dm-pre-reloc;
105-
};
106-
10797
&pinctrl_uart0 {
10898
u-boot,dm-pre-reloc;
10999
};

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