Skip to content

Commit 0c1bc17

Browse files
tinebptinebp
authored
Merge pull request #222 from MichaelJSr/simx-vpu-toggle
Toggle the RISC-V Vector Extension on and off
2 parents 01974e1 + 6d27575 commit 0c1bc17

File tree

11 files changed

+2436
-2427
lines changed

11 files changed

+2436
-2427
lines changed

‎sim/simx/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,12 +17,12 @@ CXXFLAGS += $(CONFIGS)
1717
LDFLAGS += $(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat.a
1818
LDFLAGS += -Wl,-rpath,$(THIRD_PARTY_DIR)/ramulator -L$(THIRD_PARTY_DIR)/ramulator -lramulator
1919

20-
SRCS = $(COMMON_DIR)/util.cpp $(COMMON_DIR)/mem.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/rvfloats.cpp $(COMMON_DIR)/dram_sim.cpp
20+
SRCS = $(COMMON_DIR)/util.cpp $(COMMON_DIR)/mem.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/rvfloats.cpp $(COMMON_DIR)/dram_sim.cpp
2121
SRCS += $(SRC_DIR)/processor.cpp $(SRC_DIR)/cluster.cpp $(SRC_DIR)/socket.cpp $(SRC_DIR)/core.cpp $(SRC_DIR)/emulator.cpp $(SRC_DIR)/decode.cpp $(SRC_DIR)/execute.cpp $(SRC_DIR)/func_unit.cpp $(SRC_DIR)/cache_sim.cpp $(SRC_DIR)/mem_sim.cpp $(SRC_DIR)/local_mem.cpp $(SRC_DIR)/mem_coalescer.cpp $(SRC_DIR)/dcrs.cpp $(SRC_DIR)/types.cpp
2222

2323
# Add V extension sources
2424
ifneq ($(findstring -DEXT_V_ENABLE, $(CONFIGS)),)
25-
SRCS += $(SRC_DIR)/execute_v.cpp
25+
SRCS += $(SRC_DIR)/vpu.cpp
2626
endif
2727

2828
# Debugging

‎sim/simx/arch.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@ class Arch {
2929
uint16_t num_cores_;
3030
uint16_t num_clusters_;
3131
uint16_t socket_size_;
32-
uint16_t vsize_;
3332
uint16_t num_barriers_;
3433
uint64_t local_mem_base_;
3534

@@ -40,7 +39,6 @@ class Arch {
4039
, num_cores_(num_cores)
4140
, num_clusters_(NUM_CLUSTERS)
4241
, socket_size_(SOCKET_SIZE)
43-
, vsize_(VLEN / 8)
4442
, num_barriers_(NUM_BARRIERS)
4543
, local_mem_base_(LMEM_BASE_ADDR)
4644
{}
@@ -73,10 +71,6 @@ class Arch {
7371
return socket_size_;
7472
}
7573

76-
uint16_t vsize() const {
77-
return vsize_;
78-
}
79-
8074
};
8175

8276
}

‎sim/simx/decode.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -453,6 +453,7 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
453453
if (sep++ != 0) { os << ", "; } else { os << " "; }
454454
os << "0x" << std::hex << instr.getImm() << std::dec;
455455
}
456+
#ifdef EXT_V_ENABLE
456457
if (instr.getOpcode() == Opcode::SYS && instr.getFunc3() >= 5) {
457458
// CSRs with immediate values
458459
if (sep++ != 0) { os << ", "; } else { os << " "; }
@@ -462,6 +463,7 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
462463
if (instr.getVattrMask() != 0) {
463464
print_vec_attr(os, instr);
464465
}
466+
#endif
465467
return os;
466468
}
467469
}

‎sim/simx/emulator.cpp

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,9 @@ using namespace vortex;
3333
Emulator::warp_t::warp_t(const Arch& arch)
3434
: ireg_file(arch.num_threads(), std::vector<Word>(MAX_NUM_REGS))
3535
, freg_file(arch.num_threads(), std::vector<uint64_t>(MAX_NUM_REGS))
36-
, vreg_file(MAX_NUM_REGS, std::vector<Byte>(arch.vsize()))
36+
#ifdef EXT_V_ENABLE
37+
, vreg_file(MAX_NUM_REGS, std::vector<Byte>(MAX_NUM_REGS))
38+
#endif
3739
, uuid(0)
3840
{}
3941

@@ -43,9 +45,11 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
4345
this->uuid = 0;
4446
this->fcsr = 0;
4547

48+
#ifdef EXT_V_ENABLE
4649
this->vtype = {0, 0, 0, 0, 0};
4750
this->vl = 0;
4851
this->vlmax = 0;
52+
#endif
4953

5054
for (auto& reg_file : this->ireg_file) {
5155
for (auto& reg : reg_file) {
@@ -68,6 +72,7 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
6872
}
6973
}
7074

75+
#ifdef EXT_V_ENABLE
7176
for (auto& reg_file : this->vreg_file) {
7277
for (auto& reg : reg_file) {
7378
#ifndef NDEBUG
@@ -77,16 +82,7 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
7782
#endif
7883
}
7984
}
80-
81-
for (auto& reg_file : this->vreg_file) {
82-
for (auto& reg : reg_file) {
83-
#ifndef NDEBUG
84-
reg = 0;
85-
#else
86-
reg = std::rand();
87-
#endif
88-
}
89-
}
85+
#endif
9086
}
9187

9288
///////////////////////////////////////////////////////////////////////////////
@@ -102,13 +98,17 @@ Emulator::Emulator(const Arch &arch, const DCRS &dcrs, Core* core)
10298
// considered to be big enough to hold input tiles for one output tile.
10399
// In future versions, scratchpad size should be fixed to an appropriate value.
104100
, scratchpad(std::vector<Word>(32 * 32 * 32768))
101+
#ifdef EXT_V_ENABLE
105102
, csrs_(arch.num_warps())
103+
#endif
106104
{
107105
std::srand(50);
108106

107+
#ifdef EXT_V_ENABLE
109108
for (uint32_t i = 0; i < arch_.num_warps(); ++i) {
110109
csrs_.at(i).resize(arch.num_threads());
111110
}
111+
#endif
112112

113113
this->clear();
114114
}
@@ -490,6 +490,7 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
490490
case VX_CSR_FRM: return (warps_.at(wid).fcsr >> 5);
491491
case VX_CSR_FCSR: return warps_.at(wid).fcsr;
492492

493+
#ifdef EXT_V_ENABLE
493494
// Vector CRSs
494495
case VX_CSR_VSTART:
495496
return csrs_.at(wid).at(tid)[VX_CSR_VSTART];
@@ -514,6 +515,7 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
514515
return csrs_.at(wid).at(tid)[VX_CSR_VTIME];
515516
case VX_CSR_VINSTRET:
516517
return csrs_.at(wid).at(tid)[VX_CSR_VINSTRET];
518+
#endif
517519

518520
case VX_CSR_MHARTID: return (core_->id() * arch_.num_warps() + wid) * arch_.num_threads() + tid;
519521
case VX_CSR_THREAD_ID: return tid;
@@ -631,6 +633,7 @@ void Emulator::set_csr(uint32_t addr, Word value, uint32_t tid, uint32_t wid) {
631633
csr_mscratch_ = value;
632634
break;
633635

636+
#ifdef EXT_V_ENABLE
634637
// Vector CRSs
635638
case VX_CSR_VSTART:
636639
csrs_.at(wid).at(tid)[VX_CSR_VSTART] = value;
@@ -652,6 +655,7 @@ void Emulator::set_csr(uint32_t addr, Word value, uint32_t tid, uint32_t wid) {
652655
csrs_.at(wid).at(tid)[VX_CSR_VTYPE] = value;
653656
break;
654657
case VX_CSR_VLENB: // read only, set to VLEN / 8
658+
#endif
655659

656660
case VX_CSR_SATP:
657661
#ifdef VM_ENABLE

‎sim/simx/execute.cpp

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,9 @@
2525
#include "emulator.h"
2626
#include "instr.h"
2727
#include "core.h"
28+
#ifdef EXT_V_ENABLE
2829
#include "processor_impl.h"
30+
#endif
2931
#include "VX_types.h"
3032

3133
using namespace vortex;
@@ -117,8 +119,10 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
117119
}
118120
DPN(2, "}" << std::endl);
119121
break;
122+
#ifdef EXT_V_ENABLE
120123
case RegType::Vector:
121124
break;
125+
#endif
122126
default:
123127
break;
124128
}
@@ -707,11 +711,12 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
707711
}
708712
}
709713
rd_write = true;
710-
} else {
711-
#ifdef EXT_V_ENABLE
714+
}
715+
#ifdef EXT_V_ENABLE
716+
else {
712717
this->loadVector(instr, wid, rsdata);
713-
#endif
714718
}
719+
#endif
715720
break;
716721
}
717722
case Opcode::S:
@@ -744,11 +749,12 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
744749
std::abort();
745750
}
746751
}
747-
} else {
748-
#ifdef EXT_V_ENABLE
752+
}
753+
#ifdef EXT_V_ENABLE
754+
else {
749755
this->storeVector(instr, wid, rsdata);
750-
#endif
751756
}
757+
#endif
752758
break;
753759
}
754760
case Opcode::AMO: {
@@ -932,7 +938,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
932938
for (uint32_t t = thread_start; t < num_threads; ++t) {
933939
if (!warp.tmask.test(t))
934940
continue;
935-
uint32_t frm = (func3 == 0x7) ? this->get_csr(VX_CSR_FRM, t, wid) : func3;
941+
uint32_t frm = this->get_fpu_rm(func3, t, wid);
936942
uint32_t fflags = 0;
937943
switch (func7) {
938944
case 0x00: { // RV32F: FADD.S
@@ -1247,10 +1253,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
12471253
break;
12481254
}
12491255
}
1250-
if (fflags) {
1251-
this->set_csr(VX_CSR_FCSR, this->get_csr(VX_CSR_FCSR, t, wid) | fflags, t, wid);
1252-
this->set_csr(VX_CSR_FFLAGS, this->get_csr(VX_CSR_FFLAGS, t, wid) | fflags, t, wid);
1253-
}
1256+
this->update_fcrs(fflags, t, wid);
12541257
}
12551258
rd_write = true;
12561259
break;
@@ -1304,10 +1307,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
13041307
default:
13051308
break;
13061309
}
1307-
if (fflags) {
1308-
this->set_csr(VX_CSR_FCSR, this->get_csr(VX_CSR_FCSR, t, wid) | fflags, t, wid);
1309-
this->set_csr(VX_CSR_FFLAGS, this->get_csr(VX_CSR_FFLAGS, t, wid) | fflags, t, wid);
1310-
}
1310+
this->update_fcrs(fflags, t, wid);
13111311
}
13121312
rd_write = true;
13131313
break;

‎sim/simx/main.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,9 @@ int main(int argc, char **argv) {
120120
#endif
121121
// run simulation
122122
// vector test exitcode is a special case
123+
#ifdef EXT_V_ENABLE
123124
if (vector_test) return processor.run();
125+
#endif
124126
// else continue as normal
125127
processor.run();
126128

‎sim/simx/processor.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,7 +127,9 @@ int ProcessorImpl::run() {
127127
done = false;
128128
continue;
129129
}
130+
#ifdef EXT_V_ENABLE
130131
exitcode |= cluster->get_exitcode();
132+
#endif
131133
}
132134
perf_mem_latency_ += perf_mem_pending_reads_;
133135
} while (!done);

0 commit comments

Comments
 (0)