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Merge pull request #24192 from alichraghi/fix_spirv
rename spirv backend name
2 parents 5f7780c + 872f68c commit 080ee25

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lib/std/builtin.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1121,7 +1121,7 @@ pub const CompilerBackend = enum(u64) {
11211121
stage2_sparc64 = 10,
11221122
/// The reference implementation self-hosted compiler of Zig, using the
11231123
/// spirv backend.
1124-
stage2_spirv64 = 11,
1124+
stage2_spirv = 11,
11251125
/// The reference implementation self-hosted compiler of Zig, using the
11261126
/// powerpc backend.
11271127
stage2_powerpc = 12,

lib/std/debug.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -607,7 +607,7 @@ pub fn defaultPanic(
607607
.stage2_arm,
608608
.stage2_powerpc,
609609
.stage2_riscv64,
610-
.stage2_spirv64,
610+
.stage2_spirv,
611611
.stage2_wasm,
612612
.stage2_x86,
613613
=> @trap(),

lib/std/mem.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,7 @@ const eqlBytes_allowed = switch (builtin.zig_backend) {
680680
.stage2_riscv64,
681681
=> false,
682682
// The SPIR-V backend does not support the optimized path yet.
683-
.stage2_spirv64 => false,
683+
.stage2_spirv => false,
684684
// The naive memory comparison implementation is more useful for fuzzers to
685685
// find interesting inputs.
686686
else => !builtin.fuzz,

lib/std/start.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ pub const simplified_logic = switch (builtin.zig_backend) {
1919
.stage2_arm,
2020
.stage2_powerpc,
2121
.stage2_sparc64,
22-
.stage2_spirv64,
22+
.stage2_spirv,
2323
.stage2_x86,
2424
=> true,
2525
else => false,

lib/std/testing.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ pub var log_level = std.log.Level.warn;
3535
pub const backend_can_print = switch (builtin.zig_backend) {
3636
.stage2_powerpc,
3737
.stage2_riscv64,
38-
.stage2_spirv64,
38+
.stage2_spirv,
3939
=> false,
4040
else => true,
4141
};

src/Zcu.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4585,7 +4585,7 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
45854585
.naked => true,
45864586
else => false,
45874587
},
4588-
.stage2_spirv64 => switch (cc) {
4588+
.stage2_spirv => switch (cc) {
45894589
.spirv_device, .spirv_kernel => true,
45904590
.spirv_fragment, .spirv_vertex => target.os.tag == .vulkan,
45914591
else => false,

src/Zcu/PerThread.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4386,7 +4386,7 @@ pub fn runCodegen(pt: Zcu.PerThread, func_index: InternPool.Index, air: *Air, ou
43864386
zcu.comp.config.use_llvm,
43874387
)) {
43884388
else => unreachable, // assertion failure
4389-
.stage2_spirv64,
4389+
.stage2_spirv,
43904390
.stage2_llvm,
43914391
=> {},
43924392
},

src/codegen.zig

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ fn devFeatureForBackend(backend: std.builtin.CompilerBackend) dev.Feature {
3737
.stage2_powerpc => .powerpc_backend,
3838
.stage2_riscv64 => .riscv64_backend,
3939
.stage2_sparc64 => .sparc64_backend,
40-
.stage2_spirv64 => .spirv64_backend,
40+
.stage2_spirv => .spirv64_backend,
4141
.stage2_wasm => .wasm_backend,
4242
.stage2_x86 => .x86_backend,
4343
.stage2_x86_64 => .x86_64_backend,
@@ -55,7 +55,7 @@ fn importBackend(comptime backend: std.builtin.CompilerBackend) type {
5555
.stage2_powerpc => @import("arch/powerpc/CodeGen.zig"),
5656
.stage2_riscv64 => @import("arch/riscv64/CodeGen.zig"),
5757
.stage2_sparc64 => @import("arch/sparc64/CodeGen.zig"),
58-
.stage2_spirv64 => @import("codegen/spirv.zig"),
58+
.stage2_spirv => @import("codegen/spirv.zig"),
5959
.stage2_wasm => @import("arch/wasm/CodeGen.zig"),
6060
.stage2_x86, .stage2_x86_64 => @import("arch/x86_64/CodeGen.zig"),
6161
_ => unreachable,
@@ -76,7 +76,7 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co
7676
.stage2_x86,
7777
.stage2_riscv64,
7878
.stage2_sparc64,
79-
.stage2_spirv64,
79+
.stage2_spirv,
8080
.stage2_powerpc,
8181
=> |backend| {
8282
dev.check(devFeatureForBackend(backend));

src/dev.zig

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,10 @@ pub const Env = enum {
4040
/// - `zig build-* -fno-llvm -fno-lld -target riscv64-linux`
4141
@"riscv64-linux",
4242

43+
/// - sema
44+
/// - `zig build-* -fno-llvm -fno-lld -target spirv(32/64)-* --listen=-`
45+
spirv,
46+
4347
/// - sema
4448
/// - `zig build-* -fno-llvm -fno-lld -target wasm32-* --listen=-`
4549
wasm,
@@ -178,6 +182,12 @@ pub const Env = enum {
178182
=> true,
179183
else => Env.sema.supports(feature),
180184
},
185+
.spirv => switch (feature) {
186+
.spirv64_backend,
187+
.spirv_linker,
188+
=> true,
189+
else => Env.sema.supports(feature),
190+
},
181191
.wasm => switch (feature) {
182192
.stdio_listen,
183193
.incremental,

src/target.zig

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -813,8 +813,8 @@ pub fn zigBackend(target: std.Target, use_llvm: bool) std.builtin.CompilerBacken
813813
.powerpc, .powerpcle, .powerpc64, .powerpc64le => .stage2_powerpc,
814814
.riscv64 => .stage2_riscv64,
815815
.sparc64 => .stage2_sparc64,
816-
.spirv32 => if (target.os.tag == .opencl) .stage2_spirv64 else .other,
817-
.spirv, .spirv64 => .stage2_spirv64,
816+
.spirv32 => if (target.os.tag == .opencl) .stage2_spirv else .other,
817+
.spirv, .spirv64 => .stage2_spirv,
818818
.wasm32, .wasm64 => .stage2_wasm,
819819
.x86 => .stage2_x86,
820820
.x86_64 => .stage2_x86_64,

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