Search Results for "verilog code"
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Showing 15 open source projects for "verilog code"
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wxMEdit
wxMEdit, Cross-platform Text/Hex Editor, Improved Version of MadEdit
... choices for data format copying/pasting in Hex Area •Added new feature: Paste with Overwriting in Hex Area •Improved encoding support --Added grouping of encodings --Added new encodings: ISO-8859-16,CP1258,KOI8-R/U,GB18030,CP850,CP852,CP855,CP866,CP437 for ASCII-Art •Redesigned dialogs with Code::Blocks wxSmith •Updated translations --Added Spanish,Russian,German,Polish translation --Updated Chinese and Japanese translations •Other fixes and changes -
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ALCHA
A New Programming Language for FPGA Projects
ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides. It will support an object oriented programming model, abstract data and signal types, and compile-time scripting. -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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CoolFormat
CoolFormat Source Code Formatter
CoolFormat Source Code Formatter is a code formatter for C\C++\C#\CSS\HTML\Java\JavaScript\JSON\Objective-C\PHP\SQL\Verilog\XML. It supports code highlighting for web publishment which is truly convenient for writing and reading a blog post, etc. CoolFormat source code formatting is a C\C++\C#\CSS\HTML\Java\JavaScript\JSON\PHP\SQL\XML code formatting tool. The software can quickly format in multiple styles and colorize the language. The interface adopts the style of Office 2010... -
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Project 2306 IDE Rad MacOS MCU DeveR
Electronic design and programming tools suite like Eagle, MpLab
Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned... -
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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VPreproc
C++ Verilog macro preprocessor
This is a standalone preprocessor for the Verilog HDL language. It is modified from the Verilog-PreProcessor of Verilog Perl tool 3.314. Most of the code is written by the team led by Wilson Snyder. What I have done in this project: * Provide a standalone command line interface (without Perl). * Replace the parts implemented in Perl to C++. * Encapsulate the package in a separated namespace for better independence. What I may do in the future: * Replace the C language features to C... -
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This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.
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Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )
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ANVIL - (A)(N)other (V)erilog (I)nteraction (L)evel. C++ and VPI/C code to easily instrument RTL/Verilog (dut) and C++ testbench (tb) for more powerful and efficient verification (i.e., C++/tb drives simulator).
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Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
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This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
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