Search Results for "python code generator"

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

Please note that OWFS source code, and all Issue/Tickets/merge requests have now been moved to https://github.com/owfs/owfs/. Developer mailing lists will still be kept at Sourceforge. ---- OWFS -- 1-Wire file system. Use the Dallas 1-Wire and iButton chips with standard filesystem commands. Create temperature loggers. Monitor everything. OWHTTPD -- same system, only used as a light weight web server. OWFS is also ported to embedded routers, Mac OSX and Windows. Basically you can use...

SunlightLB is an open-source 3d lattice Boltzmann code which can be used to solve a variety of hydrodynamics problems, including passive scalar transport problems.

yaucp, Yet another uController Project. Is a set of tools and source of code and information for developing for the AVR families of microcontrollers under Linux using only GPL-compatible tools, released under the GPL.

Code repository for the Laboratory for Genome Bioinformatics at Texas A&M. The LGB project was initiated primarily to support biologists at Texas A&M needing help with bioinformatics in order to use new genomic technologies.