Name | Modified | Size | Downloads / Week |
---|---|---|---|
README.txt | 2017-05-05 | 812 Bytes | |
bel_fft-0.8.tar.bz2 | 2017-05-05 | 21.5 MB | |
bel_fft_src-0.8.tar.bz2 | 2017-05-05 | 21.4 MB | |
bel_fft-Setup-0.8.exe | 2017-05-05 | 19.6 MB | |
bel_fft_src-0.7.tar.bz2 | 2013-12-14 | 36.7 MB | |
bel_fft-0.7.tar.bz2 | 2013-12-14 | 36.7 MB | |
bel_fft-Setup-0.7.exe | 2013-12-14 | 30.5 MB | |
bel_fft_src-0.6.tar.bz2 | 2013-01-02 | 1.8 MB | |
bel_fft-0.6.tar.bz2 | 2013-01-02 | 2.4 MB | |
bel_fft-Setup-0.6.exe | 2013-01-02 | 2.7 MB | |
bel_fft-Setup-0.5.exe | 2012-02-13 | 2.4 MB | |
bel_fft_src-0.5.tar.bz2 | 2012-02-13 | 1.1 MB | |
bel_fft-0.5.tar.bz2 | 2012-02-13 | 2.1 MB | |
Totals: 13 Items | 178.9 MB | 0 |
Version 0.8 - Changed reset from asynchronous to synchronous - Fix for FFTs larger than 2K words - Update for Vivado 2016.4 - Example design with PCI-Express interface for the AC701 board with Linux driver and test program. - Replaced previously delivered Vivado project with a script which generates the project. Version 0.7 - Bugfixes for AXI and Wishbone interface - Support for Xilinx Vivado IP-Integrator - Added additional AXI interface signals - Register for user bus signals - Example designs for Xilinx EDK and Vivado, connecting bel_fft to the ACP port of the Zynq processor system. Version 0.6 - Added AXI interface - New target Xilinx - Support for ISim and XSim - butterfly2 implemented - Support for Xilinx XPS - Added example design for Xilinx Zynq device Version 0.5 - Initial Version