Open Source Java Electronic Design Automation (EDA) Software for Windows

A multiplatform vector drawing program with a complete library of electronic symbols. Schematics and drawings are stored in a very compact text format. There is no netlist concept behind the drawings (so no simulation, and this is a choice) but this allows a great graphical flexibility and ease of use, making FidoCadJ the perfect tool for exchange sketches in forum and newsgroup discussions with a few clicks. Drawings can be exported in several graphic formats, such as pdf. Follow the development live on Twitter: https://twitter.com/davbucci

Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.

This is a very powerful Schematic and PCB layout tool for electronic Engineer. It is very easy to use. Coming version will add the SPICE features as well as the 3D model. This tool is target for single user, so all the things such as Schematic, PCB layout, SPICE model, 3D models are all combined into a single project file "*.prj" in ZIP file format. Anyone should able to explore and see the structure of files using any zip tool.

The aim of this project is to develop a GDSII viewer by using Java programming language. Efforts will be made especially on ease-of-use, efficiency, and capacity.

SVEditor is an Eclipse-based IDE (Integrated Development Environment) for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display.

Netsim is a mobile ad hoc network simulator targeted at large heterogeneous node configurations. It is written in Java and is easily extensible through its modular concept.

Remote Control for Embedded Device Provide an user interface for a embedded device on a PC or a mobile phone. Communication through RS232, USB, TCP_IP, Bluetooth...

ElectroMimic is an electronic circuit simulator in Java™. The simulator is focused on the piecewise-linear models normally used by undergraduate students, but can also be linked with external simulation software for more realistic results.

Analog Insydes is a Mathematica toolbox for symbolic analysis of analog electronic circuits. This project provides a set of free add-ons to Analog Insydes, including a Java front-end and a native netlister for Cadence's Analog Design Environment (ADE).

An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.

Visually build boolean logic circuits and then simulate their operation. Create custom components from user-designed circuits. Written in Java for cross-platform functionality. NOTE: This project has moved to Bitbucket at http://bitbucket.org/kwellwood/circuitsandbox

For electronics engineers, when using open source EDA tools, one of big challenge is component schematic symbols and footprints. If you are creating footprints for component with more than 100 pins, it becomes very time consuming and challenging to create error free footprints. Here is a simple program to create footprints for open source EDA kicad. The idea is to describe footprint in .csv format and convert .csv to kicad footprint format. At preset program supports Kicad only, but can be extented to support other formats.

A java based digital logic simulator, designed to be used as an educational tool. uses a GUI to allow users to quickly and easily create and visualise circuits from simple components. User can create custom components

ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.

EDAEd is Java-Based applications to demonstrate aspects of EDA (Eletronic Design Automation). This tools aim to help students of this area to view in a pratical environment, basic tools for placement and routing and data structures envolved.

Equivalence checking for two netlists of ORCAD schematic designs. Check out whether two netlists may generate the idendical PCB in later design stage, even if they are derived from different design procedures with different part-ref and siganl-name.

HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.

Virtual instrumentation software, currently designed for modifying automobile engines. Intended as a modular framework to communicate with devices on an IO port (serial, parallel etc.) and allow a visual representation of the instrument.

The official repository of JCSim is now hosted by github at https://github.com/almejo/jcsim JCSim is a fully functional Digital Circuit simulator written in Java. You can create and simulate simple (and not so simple) circuits in an easy way. It includes a basic set of gates, simple creation of new gates and simulation.

Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.

Juno - OpenVera (TM) to Jove Translator

ODog

This JAVA library give the possibility to have a CANVAS object in JAVA SWING graphical applications, including CANVAS tools such as hand-tool, linker-tool, group-tool like VISIO(TM) application. The library take advantage of Java2D packages to reach a

Generic packet visualization tool for generating flow diagrams from formatted logs. Can be used for cache coherency diagrams, software interaction diagrams or to plot network communications.

Given a simple net-list describing the high level power architecture of your system Penthode: - simulates the voltage and current from device turn on to the steady state. - highlights components working out of specification - draws a nice power tree diagram showing the currents/powers balance - plots node transient voltage and gate current waveforms It is possible to change component parameters interactively to improve the design