18 projects for "verilog code" with 2 filters applied:

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  • 1
    XLS

    XLS

    XLS: Accelerated HW Synthesis

    XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA...
    Downloads: 0 This Week
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  • 2
    wxMEdit

    wxMEdit

    wxMEdit, Cross-platform Text/Hex Editor, Improved Version of MadEdit

    ... choices for data format copying/pasting in Hex Area •Added new feature: Paste with Overwriting in Hex Area •Improved encoding support --Added grouping of encodings --Added new encodings: ISO-8859-16,CP1258,KOI8-R/U,GB18030,CP850,CP852,CP855,CP866,CP437 for ASCII-Art •Redesigned dialogs with Code::Blocks wxSmith •Updated translations --Added Spanish,Russian,German,Polish translation --Updated Chinese and Japanese translations •Other fixes and changes
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    Downloads: 191 This Week
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  • 3
    ALCHA

    ALCHA

    A New Programming Language for FPGA Projects

    ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides. It will support an object oriented programming model, abstract data and signal types, and compile-time scripting.
    Downloads: 0 This Week
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  • 4
    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
    Downloads: 0 This Week
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  • Build Securely on AWS with Proven Frameworks Icon
    Build Securely on AWS with Proven Frameworks

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  • 5
    Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
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    Downloads: 12 This Week
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  • 6
    DRAKON Editor

    DRAKON Editor

    A free cross-platform editor for the DRAKON visual language.

    DRAKON is a diagram language developed within the Russian space program. Its primary objective is presenting complex software systems in a way which is easy to understand by humans. DRAKON's motto: took a glance - understood at once. DRAKON Editor helps software architects, quality specialists and developers. Architects and quality assurers can express a high-level view of how their product works. DRAKON serves them to explain the dynamics of a software system. Software engineers can use...
    Downloads: 38 This Week
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  • 7
    adms
    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
    Downloads: 9 This Week
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  • 8
    Project 2306 IDE Rad MacOS MCU DeveR

    Project 2306 IDE Rad MacOS MCU DeveR

    Electronic design and programming tools suite like Eagle, MpLab

    Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned...
    Downloads: 0 This Week
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  • 9

    PLP

    Powerfull pre-processor

    Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
    Downloads: 0 This Week
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  • Build Securely on Azure with Proven Frameworks Icon
    Build Securely on Azure with Proven Frameworks

    Lay a foundation for success with Tested Reference Architectures developed by Fortinet’s experts. Learn more in this white paper.

    Moving to the cloud brings new challenges. How can you manage a larger attack surface while ensuring great network performance? Turn to Fortinet’s Tested Reference Architectures, blueprints for designing and securing cloud environments built by cybersecurity experts. Learn more and explore use cases in this white paper.
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  • 10
    Qfsm

    Qfsm

    A graphical Finite State Machine (FSM) designer.

    A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
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    Downloads: 13 This Week
    Last Update:
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  • 11

    ApproxAdderLib

    Library of Approximate Adders

    We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well...
    Downloads: 0 This Week
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  • 12
    VHDT

    VHDT

    VHDL Design Tool - code generation and project management

    Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation.
    Downloads: 2 This Week
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  • 13
    Application defines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
    Downloads: 0 This Week
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  • 14
    Covered
    Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
    Downloads: 16 This Week
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  • 15
    vMAGIC
    vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
    Downloads: 0 This Week
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  • 16
    pprint - cross referencing postscript pretty-printer for C/C++/Verilog source code
    Downloads: 0 This Week
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  • 17
    Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
    Downloads: 0 This Week
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  • 18
    This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
    Downloads: 0 This Week
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