Search Results for "blowfish algorithm in verilog"

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Showing 4 open source projects for "blowfish algorithm in verilog"

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    Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai
    Downloads: 4 This Week
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  • 2
    BlowfishVHDL - free fully synthesizable Blowfish encryption algorithm hardware implementation.
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    Downloads: 0 This Week
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  • 3
    A Verilog design for a simple ASIC that executes the Ray Tracing Algorithm.
    Downloads: 0 This Week
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  • 4
    The H.264 VHDL core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. Simple, fully synchronous design with low gate count.
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    Downloads: 0 This Week
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