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  • Tbilisi, Georgia
  • 06:08 (UTC +04:00)

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Starred repositories

3 stars written in Verilog
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RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Verilog 326 51 Updated Jan 23, 2022

Cλash/Haskell FPGA-based SKI calculus evaluator

Verilog 49 3 Updated Jan 9, 2016

Modeling the WW2 Enigma crypto machine in Cryptol and Bluespec BSV

Verilog 8 Updated Jul 17, 2016