Bug#34594825 NdbSpin_Init calculates wrong number of loops in NdbSpin

Clean up the cpu_pause definitions in the HW abstraction layer mt-asm.h:

Fixes two related cpu_pause issues:

1) Empty (and unused) definitions for cpu_pause() where provided
   for platforms which didn't #define NDB_HAVE_CPU_PAUSE
  - GNUC compiling code for __sparc
  - SUN STUDIO compiling code for __sparc

2) For ARM architecture '__aarch64__' (Apple M1/M2) an implementation of
   cpu_pause() was provided. As it didn't also #define NDB_HAVE_CPU_PAUSE
   the 'pause' was unused. Thus, usage of spin was effectively disabled
   on that platform.

Change-Id: I9e1bd11f26ea861240be4753cadbb58e72f29fd9

Author: Ole John Aske

storage/ndb/include/portlib/mt-asm.h

@@ -107,10 +107,8 @@ xcng(volatile unsigned * addr, int val)
   asm volatile("membar #StoreLoad | #StoreStore");
   return ret;
 }
-#define cpu_pause()
 #define NDB_HAVE_XCNG
 #else
-#define cpu_pause()
 /* link error if used incorrectly (i.e wo/ having NDB_HAVE_XCNG) */
 extern  int xcng(volatile unsigned * addr, int val);
 #endif
@@ -150,6 +148,7 @@ xcng(volatile unsigned * addr, int val)
 #define NDB_HAVE_RMB
 #define NDB_HAVE_WMB
 //#define NDB_HAVE_XCNG
+#define NDB_HAVE_CPU_PAUSE
 
 #define mb() std::atomic_thread_fence(std::memory_order_seq_cst)
 #define rmb() std::atomic_thread_fence(std::memory_order_seq_cst)