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Description
For a gowin FPGA, I was trying a simple ring adder like this:
// counter.v
module counter
(
input clk,
output [5:0] led
);
localparam WAIT_TIME = 2700000;
reg [5:0] ledCounter = 0;
reg [23:0] clockCounter = 0;
always @(posedge clk) begin
clockCounter <= clockCounter + 1;
if (clockCounter == WAIT_TIME) begin
clockCounter <= 0;
if (ledCounter == 0)
ledCounter <= 1;
else
ledCounter <= ledCounter << 1;
end
end
assign led = ~ledCounter;
endmoduleThe constraints file tangnano9k.cst is:
IO_LOC "clk" 52;
IO_PORT "clk" PULL_MODE=UP;
IO_LOC "led[0]" 10;
IO_LOC "led[1]" 11;
IO_LOC "led[2]" 13;
IO_LOC "led[3]" 14;
IO_LOC "led[4]" 15;
IO_LOC "led[5]" 16;
The following commands worked:
$ yosys -p "read_verilog counter.v; synth_gowin -top counter -json counter.json"
$ nextpnr-gowin --json counter.json --freq 27 --write counter_pnr.json \
--device GW1NR-LV9QN88PC6/I5 --family GW1N-9C --cst tangnano9k.cst
and gave
Max frequency for clock 'clk_IBUF_I_O': 290.53 MHz (PASS at 27.00 MHz)
But when I tried nextpnr-himbaechel instead of nextpnr-gowin, it
gave this message: No Fmax available; no interior timing paths found in design
The command used was:
nextpnr-himbaechel --json counter.json --freq 27 --write counter_pnr.json \
--device GW1NR-LV9QN88PC6/I5 -l pnr.log --report report.json \
--vopt family=GW1N-9C --vopt cst=tangnano9k.cst \
--placed-svg placed.svg \
--routed-svg routed.svg
Any idea why this is happening?
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