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addymoll98addymoll98
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Merge pull request #14 from addymoll98/Adeline
a few more updates on pipeline, not 100% yet
2 parents 2b9d9cc + a28c01e commit 1e11c0f

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-39
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3 files changed

+40
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‎a.exe‎

-6.95 KB
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‎instruction.txt‎

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,13 @@
1-
FMUL.D F8,F2,F1
2-
FADD.D F2,F1,F8
3-
FSUB.D F7,F8,F10
4-
FDIV.D F1,F2,F8
5-
FDIV.D F2,F2,F2
1+
FLD F4,2000(X0)
2+
FSD F4,4000(X0)
3+
LD X1,1000(X0)
4+
SD X1,1000(X0)
5+
FADD.D F2,F4,F6
6+
FSUB.D F8,F8,F10
7+
FMUL.D F8,F8,F4
8+
FDIV.D F8,F8,F4
9+
FSD F8,6000(X0)
10+
ADD X1,X2,X3
11+
SUB X1,X1,X3
12+
ADDI X2,X4,1
13+
SUBI X1,X2,1

‎project1.cpp‎

Lines changed: 27 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -736,7 +736,7 @@ int issue(vector<Instruction>& inst1, vector<reservationStation>& resstation1, v
736736
}*/
737737

738738
//execute with loop
739-
void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1, vector<registerStatus>& regstatus1, vector<int>& reg1, int FPMUL, int FPDIV, int FPADD, int FPLD, int FPALU, int LDINT, int INT,int lst, int led, vector<string>& STRING_INST1, vector<Instruction> INST_AFTERLOOP, vector<int> FUstatus)
739+
void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1, vector<registerStatus>& regstatus1, vector<int>& reg1, int FPMUL, int FPDIV, int FPADD, int FPLD, int FPALU, int LDINT, int INT,int lst, int led, vector<string>& STRING_INST1, vector<Instruction> INST_AFTERLOOP, vector<int>& FUstatus)
740740
{
741741

742742

@@ -767,25 +767,23 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
767767
if (inst1[resstation1[i].instNum].executeClockBegin == 0)// check if the executeclockbegin is having default value. Use instNum variable find the instruction number
768768
{
769769
inst1[resstation1[i].instNum].executeClockBegin = Clock;// if it is issue the current clock value as execution start cycle
770-
if(resstation1[i].op==0 || resstation1[i].op==1)
771-
FUstatus[0]=Clock;
772-
if(resstation1[i].op==2)
773-
FUstatus[1]=Clock;
774-
if(resstation1[i].op==3)
775-
FUstatus[2]=Clock;
776-
if((resstation1[i].op==4 || resstation1[i].op==5)&&FUstatus[3]==-1)
777-
FUstatus[3]=Clock;
778-
if(resstation1[i].op==6 || resstation1[i].op==7|| resstation1[i].op==8|| resstation1[i].op==9|| resstation1[i].op==10|| resstation1[i].op==11)
779-
FUstatus[4]=Clock;
770+
if(resstation1[i].op==0 || resstation1[i].op==1) //if FADD or FSUB
771+
FUstatus[0]=Clock+FPADD; //Adder functional unit is 4 cc
772+
if(resstation1[i].op==2) //FMUL
773+
FUstatus[1]=Clock+FPMUL; //FMUL.D functional unit is 7 cc
774+
if(resstation1[i].op==3) //FDIV
775+
FUstatus[2]=Clock+FPDIV; //Divider fuctional unit is 24 cc
776+
if((resstation1[i].op==4 || resstation1[i].op==5)&&FUstatus[3]==-1) //FLD/FSD
777+
FUstatus[3]=Clock+FPLD;
778+
if(resstation1[i].op==6 || resstation1[i].op==7|| resstation1[i].op==8|| resstation1[i].op==9|| resstation1[i].op==10|| resstation1[i].op==11) //int functional unit
779+
FUstatus[4]=Clock+INT; //int functional unit is 1 cc
780780
}
781781
resstation1[i].lat++;// Increment the latency to match the latency of FMUL,FADD,FSUB etc. If latency matches means that we can perform the execution
782782
int temp_operation = resstation1[i].op; // store operation type
783783
if (temp_operation == 0)// means FADD Operation
784784
{
785785
if (resstation1[i].lat == FPADD)
786786
{
787-
//set functional unit to not busy
788-
FUstatus[0]=-1;
789787
//perform addition
790788
resstation1[i].result = resstation1[i].Vj + resstation1[i].Vk;
791789
//we can now complete the execution and update the resultReady flag
@@ -803,8 +801,6 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
803801
{
804802
if (resstation1[i].lat == FPADD)
805803
{
806-
//set functional unit to clock cycle
807-
FUstatus[0]=-1;
808804
//perform subtraction
809805
resstation1[i].result = resstation1[i].Vj - resstation1[i].Vk;
810806
//we can now complete the execution and update the resultReady flag
@@ -822,8 +818,6 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
822818
{
823819
if (resstation1[i].lat == FPMUL)
824820
{
825-
//set functional unit to clock cycle
826-
FUstatus[1]=-1;
827821
//perform multiplication
828822
resstation1[i].result = resstation1[i].Vj * resstation1[i].Vk;
829823
//we can now complete the execution and update the resultReady flag
@@ -841,8 +835,6 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
841835
{
842836
if (resstation1[i].lat == FPDIV)
843837
{
844-
//set functional unit to clock cycle
845-
FUstatus[2]=-1;
846838
//perfrom division
847839
resstation1[i].result = resstation1[i].Vj / resstation1[i].Vk;
848840
//we can now complete the execution and update the resultReady flag
@@ -861,8 +853,6 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
861853
{
862854
if (resstation1[i].lat == FPALU)
863855
{
864-
//set functional unit to clock cycle
865-
FUstatus[3]=-1;
866856
resstation1[i].result = resstation1[i].Vj;
867857
//we can now complete the execution and update the resultReady flag
868858
resstation1[i].resultReady = true;
@@ -881,8 +871,6 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
881871
{
882872
if (resstation1[i].lat == FPALU)
883873
{
884-
//set functional unit to clock cycle
885-
FUstatus[3]=-1;
886874
resstation1[i].result = resstation1[i].Vj;
887875
//we can now complete the execution and update the resultReady flag
888876
resstation1[i].resultReady = true;
@@ -900,8 +888,6 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
900888
{
901889
if (resstation1[i].lat - 1 == INT) // by default lat will start in 1. Since value for Inetger operations is zero we do -1 to avoid infinite loop scenario.
902890
{
903-
//set functional unit to clock cycle
904-
FUstatus[4]=-1;
905891
//perform addition
906892
if (temp_operation == 6)
907893
{
@@ -930,8 +916,6 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
930916
{
931917
if (resstation1[i].lat - 1 == INT) // by default lat will start in 1. Since value for Inetger operations is zero we do -1 to avoid infinite loop scenario.
932918
{
933-
//set functional unit to clock cycle
934-
FUstatus[4]=-1;
935919
//perform subtraction
936920
if (temp_operation == 7)
937921
{
@@ -961,8 +945,6 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
961945
{
962946
if (resstation1[i].lat == LDINT)
963947
{
964-
//set functional unit to clock cycle
965-
FUstatus[4]=-1;
966948
resstation1[i].result = resstation1[i].Vj;
967949
//we can now complete the execution and update the resultReady flag
968950
resstation1[i].resultReady = true;
@@ -980,8 +962,6 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
980962
{
981963
if (resstation1[i].lat - 1 == INT)
982964
{
983-
//set functional unit to clock cycle
984-
FUstatus[4]=-1;
985965
resstation1[i].result = resstation1[i].Vj;
986966
//we can now complete the execution and update the resultReady flag
987967
resstation1[i].resultReady = true;
@@ -1114,11 +1094,24 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
11141094
}
11151095
//now that any possible instructions have begin execution reset all funcitonal units but divide to available if Pipelined
11161096
cout<<FUstatus[0]<<" "<<FUstatus[1]<<" "<<FUstatus[2]<<" "<<FUstatus[3]<<" "<<FUstatus[4]<<" "<<endl;
1117-
if (Pipelined==true){
1097+
if (Pipelined==true){ //If pipelined, reset all to available for next cc except divider
11181098
FUstatus[0]=-1;
11191099
FUstatus[1]=-1;
11201100
FUstatus[3]=-1;
11211101
FUstatus[4]=-1;
1102+
if (FUstatus[2]==Clock){
1103+
FUstatus[2]=-1;
1104+
}
1105+
cout<<"reseting the fu in pipeline true if"<<endl;
1106+
}
1107+
else { //otherwise, set to available if they ended execution this cc
1108+
for (int i=0; i<5; i++){
1109+
if (FUstatus[i]==Clock){
1110+
FUstatus[i]=-1;
1111+
cout<<"resetting fu for "<< i<<" in pipeline false if"<<endl;
1112+
}
1113+
}
1114+
11221115
}
11231116
}
11241117

@@ -1580,13 +1573,13 @@ int main()
15801573
issue(inst, resStation, registerStatus, registers,operation);
15811574
execute(inst, resStation, registerStatus, registers, FPMUL, FPDIV, FPADD, FPLD, FPALU, LDINT, INT,looplinestart,looplinened,string_inst,inst_afterloop,FUstatus);
15821575
writeback(inst, resStation, registerStatus, registers);
1583-
1576+
15841577
//print cc table
15851578
//printRegisters(registers);
15861579
if(!loopclock)
15871580
printclockcycletable(inst,string_inst);
15881581
//std::cout << "inst" << inst.size();
1589-
std::cout << "Total Writebacks" << Total_WRITEBACKS;
1582+
//std::cout << "Total Writebacks" << Total_WRITEBACKS;
15901583
//std::cout << "Total Writebacks" << Total_WRITEBACKS;
15911584

15921585
// Check if all reservation stations are empty -> program done

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