Add default_nettype none and resetall directives

Author: alexforencich

rtl/arbiter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Arbiter module
@@ -153,3 +155,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 width adapter
@@ -318,3 +320,5 @@ axi_adapter_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axi_adapter_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 width adapter
@@ -690,3 +692,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_adapter_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 width adapter
@@ -781,3 +783,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_axil_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 to AXI4-Lite adapter
@@ -217,3 +219,5 @@ axi_axil_adapter_rd_inst (
 );
 
 endmodule
+
+`resetall

rtl/axi_axil_adapter_rd.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 to AXI4-Lite adapter (read)
@@ -504,3 +506,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_axil_adapter_wr.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 to AXI4-Lite adapter (write)
@@ -558,3 +560,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_cdma.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 Central DMA
@@ -792,3 +794,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_cdma_desc_mux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI CDMA descriptor mux
@@ -259,3 +261,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axi_crossbar.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4 crossbar
@@ -385,3 +387,5 @@ axi_crossbar_rd_inst (
 );
 
 endmodule
+
+`resetall