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Pull requests: alexforencich/verilog-axi

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Pull requests list

Updated AXI-lite RAM to pass a formal verification check
#11 opened Nov 6, 2020 by ZipCPU Loading…
1
Add explicit python3 prefix to all python paths in test suite
#62 opened Dec 7, 2023 by dbarrie Loading…
Fix readme typo
#27 opened Oct 12, 2021 by FlyGoat Loading…
Prevent CL_M_COUNT-1 from being -1
#87 opened Dec 5, 2024 by offnaria Loading…
1
add option for initialization file for RAM
#42 opened Dec 18, 2022 by bunnie Loading…
WIP: Verilator Compatibility
#47 opened Mar 1, 2023 by benreynwar Loading…
fix numerical overflow in bit shift operation
#41 opened Dec 18, 2022 by bunnie Loading…
Fix AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET part select
#49 opened Mar 5, 2023 by AlexLao512 Loading…
6
Fix crossbar locking up after reading to write-only address
#85 opened Dec 3, 2024 by aharrysrc Loading…
1
Add standalone Verilog testbench for axi_ram (write/read verification)
#90 opened Nov 2, 2025 by LeonidasY-coder Loading…
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