Lab5 - Correct skeleton code set.

Author: carotinoid

Lab05/Lab5-skeleton/ALU.v

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+`include "alu_op.v"
+
+module ALU (input [7:0] alu_op,
+            input [31:0] alu_in_1,
+            input [31:0] alu_in_2,
+            output reg [31:0] alu_result,
+            output alu_bcond);
+
+always @(*) begin
+    alu_bcond = 0;
+    alu_result = 0;
+    case(alu_op) 
+        `ADD : alu_result = alu_in_1 + alu_in_2;
+        `SUB : alu_result = alu_in_1 - alu_in_2;
+        `SLL : alu_result = alu_in_1 << alu_in_2;
+        `XOR : alu_result = alu_in_1 ^ alu_in_2;
+        `OR : alu_result = alu_in_1 | alu_in_2;
+        `AND : alu_result = alu_in_1 & alu_in_2;
+        `SRL : alu_result = alu_in_1 >> alu_in_2;
+        `SRA : alu_result = alu_in_1 >>> alu_in_2;
+        `BEQ : if(alu_in_1 == alu_in_2) alu_bcond = 1;
+        `BNE : if(alu_in_1 != alu_in_2) alu_bcond = 1;
+        `BLT : if(alu_in_1 < alu_in_2) alu_bcond = 1;
+        `BGE : if(alu_in_1 >= alu_in_2) alu_bcond = 1;
+        default: alu_result = 0;
+    endcase
+end
+
+endmodule

Lab05/Lab5-skeleton/ALUControlUnit.v

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+`include "alu_op.v"
+`include "opcodes.v"
+
+module ALUControlUnit(input [31:0] instr,
+                     output reg [7:0] alu_op);
+
+    wire [6:0] opcode = instr[6:0];
+    wire [2:0] funct3 = instr[14:12];
+    wire Instr30 = instr[30];
+
+    wire [6:0] funct7;
+    assign funct7 = {1'b0, Instr30, 5'b00000};
+
+    always @(*) begin
+        case(opcode)
+            `ARITHMETIC : begin
+                case(funct3) 
+                    `FUNCT3_ADD : begin // with `FUNCT7_SUB
+                        if(funct7 == `FUNCT7_SUB) alu_op = `SUB;
+                        else alu_op = `ADD;
+                    end
+                    `FUNCT3_SLL : alu_op = `SLL;    
+                    `FUNCT3_XOR : alu_op = `XOR;    
+                    `FUNCT3_OR : alu_op = `OR;    
+                    `FUNCT3_AND : alu_op = `AND;    
+                    `FUNCT3_SRL : alu_op = `SRL;  
+                    default: alu_op = `ADD;  
+                endcase
+            end
+            `ARITHMETIC_IMM : begin
+                case(funct3)
+                    `FUNCT3_ADD : alu_op = `ADD;
+                    `FUNCT3_SLL : alu_op = `SLL;
+                    `FUNCT3_XOR : alu_op = `XOR;
+                    `FUNCT3_OR : alu_op = `OR;
+                    `FUNCT3_AND : alu_op = `AND;
+                    `FUNCT3_SRL : alu_op = `SRL;
+                    default: alu_op = `ADD;
+                endcase
+            end
+            `LOAD, `STORE, `JALR : begin
+                alu_op = `ADD;
+            end
+            `BRANCH : begin
+                case(funct3)
+                    `FUNCT3_BEQ : alu_op = `BEQ;
+                    `FUNCT3_BNE : alu_op = `BNE;
+                    `FUNCT3_BLT : alu_op = `BLT;
+                    `FUNCT3_BGE : alu_op = `BGE;
+                    default: alu_op = `BEQ;
+                endcase
+            end
+            default: alu_op = `ADD;
+        endcase
+    end
+    
+endmodule

Lab05/Lab5-skeleton/Adder.v

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+module Adder(input [31:0] in0, 
+           input [31:0] in1, 
+           output [31:0] out);
+
+    assign out = in0 + in1;
+    
+endmodule

Lab05/Lab5-skeleton/BranchPredictUnit.v

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+module BranchPredictUnit(
+    input [31:0] current_pc,
+    output[31:0] predict_pc,
+    input        clk,
+    input        reset,
+
+    input        update,
+    input [31:0] faux_pas_pc,
+    input        actual_behavior
+);
+
+wire [24:0] tag = current_pc[31:7];
+wire [4:0] index = current_pc[6:2];
+
+reg [24:0] tag_table[0:31];
+reg [31:0] BTB[0:31];
+reg [4:0] BHSR;
+reg [1:0] PHT[0:31];
+
+wire [24:0] upd_tag = faux_pas_pc[31:7];
+wire [4:0] upd_index = faux_pas_pc[6:2];
+
+
+always @(posedge clk) begin
+    if (reset) begin
+        BHSR <= 5'b0;
+        for (integer i = 0; i < 32; i = i + 1) begin
+            tag_table[i] <= 25'b0;
+            BTB[i] <= 32'b0;
+            PHT[i] <= 2'b00;
+        end
+    end
+    else if(update) begin
+        BHSR <= {BHSR[3:0], actual_behavior};
+        tag_table[upd_index] <= upd_tag;
+        BTB[upd_index] <= faux_pas_pc;
+        if (actual_behavior) begin
+            if (PHT[upd_index ^ BHSR] < 2'b11) begin
+                PHT[upd_index ^ BHSR] <= PHT[upd_index ^ BHSR] + 1;
+            end
+        end 
+        else begin
+            if (PHT[upd_index ^ BHSR] > 2'b00) begin
+                PHT[upd_index ^ BHSR] <= PHT[upd_index ^ BHSR] - 1;
+            end
+        end
+    end
+end
+
+/* Gshare */
+assign predict_pc = (tag == tag_table[index]) && (PHT[index ^ BHSR] > 2'b01) ? BTB[index] : current_pc + 4;
+
+/* always not taken */
+// assign predict_pc = current_pc + 4; 
+
+/* always taken */
+// assign predict_pc = (tag == tag_table[index]) ? BTB[index] : current_pc + 4;
+
+endmodule

Lab05/Lab5-skeleton/BubbleGen.v

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+module BubbleGen(
+    // input taken,
+    // input hit,
+    input IF_wrong,
+    input ID_wrong,
+    input EX_wrong,
+    output IF_is_bubble,
+    output ID_is_bubble
+);
+
+assign ID_is_bubble = EX_wrong;
+assign IF_is_bubble = EX_wrong || ID_wrong;
+// assign isbubble = taken ^ hit;
+
+endmodule

Lab05/Lab5-skeleton/ControlUnit.v

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+`include "opcodes.v"
+
+module ControlUnit (input [6:0] Instr,
+                     output MemRead,
+                     output MemtoReg,
+                     output MemWrite,
+                     output ALUSrc,
+                     output RegWrite,
+                     output PCtoReg,
+                     output Branch,
+                     output JAL,
+                     output JALR,
+                     output is_ecall);
+
+assign MemRead = (Instr == `LOAD);
+assign MemtoReg = (Instr == `LOAD);
+assign MemWrite = (Instr == `STORE);
+assign ALUSrc = (Instr != `ARITHMETIC) && (Instr != `BRANCH);
+assign RegWrite = (Instr != `STORE) && (Instr != `BRANCH);
+assign PCtoReg = (Instr == `JAL) || (Instr == `JALR);
+
+assign Branch = (Instr == `BRANCH);
+assign JAL = (Instr == `JAL);
+assign JALR = (Instr == `JALR);
+
+assign is_ecall = (Instr == `ECALL);
+
+endmodule

Lab05/Lab5-skeleton/ControlflowDetectUnit.v

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+`include "opcodes.v"
+
+module ControlflowDetectUnit(
+    input [6:0] Instr,
+    output is_ctrlflow
+);
+
+assign is_ctrlflow = (Instr == `BRANCH) || (Instr == `JAL) || (Instr == `JALR);
+
+endmodule

Lab05/Lab5-skeleton/DataForwardingUnit.v

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+module DataForwardingUnit (
+    input [4:0] ID_EX_rs1,
+    input [4:0] ID_EX_rs2,
+    input [4:0] EX_MEM_rd,
+    input [4:0] MEM_WB_rd,
+    input EX_MEM_reg_write,
+    input MEM_WB_reg_write,
+    input ID_ctrl_is_ecall,
+    output [1:0] forward_a,
+    output [1:0] forward_b,
+    output forward_ecall
+);
+
+    assign forward_a = (ID_EX_rs1 != 0 && ID_EX_rs1 == EX_MEM_rd && EX_MEM_reg_write) ? 2'b10 :
+                       (ID_EX_rs1 != 0 && ID_EX_rs1 == MEM_WB_rd && MEM_WB_reg_write) ? 2'b01 :
+                        2'b00;
+    assign forward_b = (ID_EX_rs2 != 0 && ID_EX_rs2 == EX_MEM_rd && EX_MEM_reg_write) ? 2'b10 :
+                       (ID_EX_rs2 != 0 && ID_EX_rs2 == MEM_WB_rd && MEM_WB_reg_write) ? 2'b01 :
+                        2'b00;
+    assign forward_ecall = ID_ctrl_is_ecall && (EX_MEM_rd == 17) && EX_MEM_reg_write;
+endmodule

Lab05/Lab5-skeleton/HazardDetectionUnit.v

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+`include "opcodes.v"
+
+module HazardDetectionUnit(
+    input [6:0] opcode,
+    input [4:0] ID_rs1,
+    input [4:0] ID_rs2,
+    input [4:0] ID_EX_rd,
+    input ID_EX_mem_read,
+    input ID_ctrl_is_ecall,
+    output PC_Write,
+    output IF_ID_Write,
+    output ID_CtrlUnitMux_sel
+);
+
+wire use_rs1 = ID_rs1 != 0 && ((opcode == `ARITHMETIC) || (opcode == `ARITHMETIC_IMM) || (opcode == `LOAD) || (opcode == `STORE) || (opcode == `BRANCH));
+wire use_rs2 = ID_rs2 != 0 && ((opcode == `ARITHMETIC) || (opcode == `STORE) || (opcode == `BRANCH));
+
+wire stall = (ID_ctrl_is_ecall && ID_EX_rd == ID_rs1) || (ID_EX_mem_read && (((ID_EX_rd == ID_rs1) && (use_rs1) || ((ID_EX_rd == ID_rs2) && (use_rs2)))));
+
+assign PC_Write = !stall;
+assign IF_ID_Write = !stall;
+assign ID_CtrlUnitMux_sel = stall;
+
+endmodule

Lab05/Lab5-skeleton/ImmediateGenerator.v

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+`include "opcodes.v"
+
+module ImmediateGenerator (input [31:0] Instr,
+                output reg [31:0] imm_gen_out);
+
+wire [6:0] op = Instr[6:0];
+
+initial begin
+    imm_gen_out = 0;
+end
+
+
+always @(*) begin
+    imm_gen_out = 0;
+    case(op)
+        `ARITHMETIC_IMM, `LOAD, `JALR: begin
+            imm_gen_out[11:0] = Instr[31:20];
+            imm_gen_out[31:12] = {20{imm_gen_out[11]}};
+        end
+        `STORE : begin
+            imm_gen_out[4:0] = Instr[11:7];
+            imm_gen_out[11:5] = Instr[31:25];
+            imm_gen_out[31:12] = {20{imm_gen_out[11]}};
+        end
+        `JAL : begin
+            imm_gen_out[10:1] = Instr[30:21];
+            imm_gen_out[11] = Instr[20];
+            imm_gen_out[19:12] = Instr[19:12];
+            imm_gen_out[20] = Instr[31];
+            imm_gen_out[31:21] = {11{imm_gen_out[20]}};
+        end
+        `BRANCH : begin
+            imm_gen_out[4:1] = Instr[11:8];
+            imm_gen_out[10:5] = Instr[30:25];
+            imm_gen_out[11] = Instr[7];
+            imm_gen_out[12] = Instr[31];
+            imm_gen_out[31:13] = {19{imm_gen_out[12]}};
+        end
+        default: imm_gen_out = 0;
+    endcase
+end
+
+
+endmodule