@@ -3983,54 +3983,6 @@ static void i830_update_wm(struct drm_device *dev)
39833983#define ILK_LP0_PLANE_LATENCY 700
39843984#define ILK_LP0_CURSOR_LATENCY 1300
39853985
3986- static bool ironlake_compute_wm0 (struct drm_device * dev ,
3987- int pipe ,
3988- const struct intel_watermark_params * display ,
3989- int display_latency_ns ,
3990- const struct intel_watermark_params * cursor ,
3991- int cursor_latency_ns ,
3992- int * plane_wm ,
3993- int * cursor_wm )
3994- {
3995- struct drm_crtc * crtc ;
3996- int htotal , hdisplay , clock , pixel_size ;
3997- int line_time_us , line_count ;
3998- int entries , tlb_miss ;
3999-
4000- crtc = intel_get_crtc_for_pipe (dev , pipe );
4001- if (crtc -> fb == NULL || !crtc -> enabled )
4002- return false;
4003-
4004- htotal = crtc -> mode .htotal ;
4005- hdisplay = crtc -> mode .hdisplay ;
4006- clock = crtc -> mode .clock ;
4007- pixel_size = crtc -> fb -> bits_per_pixel / 8 ;
4008-
4009- /* Use the small buffer method to calculate plane watermark */
4010- entries = ((clock * pixel_size / 1000 ) * display_latency_ns ) / 1000 ;
4011- tlb_miss = display -> fifo_size * display -> cacheline_size - hdisplay * 8 ;
4012- if (tlb_miss > 0 )
4013- entries += tlb_miss ;
4014- entries = DIV_ROUND_UP (entries , display -> cacheline_size );
4015- * plane_wm = entries + display -> guard_size ;
4016- if (* plane_wm > (int )display -> max_wm )
4017- * plane_wm = display -> max_wm ;
4018-
4019- /* Use the large buffer method to calculate cursor watermark */
4020- line_time_us = ((htotal * 1000 ) / clock );
4021- line_count = (cursor_latency_ns / line_time_us + 1000 ) / 1000 ;
4022- entries = line_count * 64 * pixel_size ;
4023- tlb_miss = cursor -> fifo_size * cursor -> cacheline_size - hdisplay * 8 ;
4024- if (tlb_miss > 0 )
4025- entries += tlb_miss ;
4026- entries = DIV_ROUND_UP (entries , cursor -> cacheline_size );
4027- * cursor_wm = entries + cursor -> guard_size ;
4028- if (* cursor_wm > (int )cursor -> max_wm )
4029- * cursor_wm = (int )cursor -> max_wm ;
4030-
4031- return true;
4032- }
4033-
40343986/*
40353987 * Check the wm result.
40363988 *
@@ -4139,12 +4091,12 @@ static void ironlake_update_wm(struct drm_device *dev)
41394091 unsigned int enabled ;
41404092
41414093 enabled = 0 ;
4142- if (ironlake_compute_wm0 (dev , 0 ,
4143- & ironlake_display_wm_info ,
4144- ILK_LP0_PLANE_LATENCY ,
4145- & ironlake_cursor_wm_info ,
4146- ILK_LP0_CURSOR_LATENCY ,
4147- & plane_wm , & cursor_wm )) {
4094+ if (g4x_compute_wm0 (dev , 0 ,
4095+ & ironlake_display_wm_info ,
4096+ ILK_LP0_PLANE_LATENCY ,
4097+ & ironlake_cursor_wm_info ,
4098+ ILK_LP0_CURSOR_LATENCY ,
4099+ & plane_wm , & cursor_wm )) {
41484100 I915_WRITE (WM0_PIPEA_ILK ,
41494101 (plane_wm << WM0_PIPE_PLANE_SHIFT ) | cursor_wm );
41504102 DRM_DEBUG_KMS ("FIFO watermarks For pipe A -"
@@ -4153,12 +4105,12 @@ static void ironlake_update_wm(struct drm_device *dev)
41534105 enabled |= 1 ;
41544106 }
41554107
4156- if (ironlake_compute_wm0 (dev , 1 ,
4157- & ironlake_display_wm_info ,
4158- ILK_LP0_PLANE_LATENCY ,
4159- & ironlake_cursor_wm_info ,
4160- ILK_LP0_CURSOR_LATENCY ,
4161- & plane_wm , & cursor_wm )) {
4108+ if (g4x_compute_wm0 (dev , 1 ,
4109+ & ironlake_display_wm_info ,
4110+ ILK_LP0_PLANE_LATENCY ,
4111+ & ironlake_cursor_wm_info ,
4112+ ILK_LP0_CURSOR_LATENCY ,
4113+ & plane_wm , & cursor_wm )) {
41624114 I915_WRITE (WM0_PIPEB_ILK ,
41634115 (plane_wm << WM0_PIPE_PLANE_SHIFT ) | cursor_wm );
41644116 DRM_DEBUG_KMS ("FIFO watermarks For pipe B -"
@@ -4223,10 +4175,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
42234175 unsigned int enabled ;
42244176
42254177 enabled = 0 ;
4226- if (ironlake_compute_wm0 (dev , 0 ,
4227- & sandybridge_display_wm_info , latency ,
4228- & sandybridge_cursor_wm_info , latency ,
4229- & plane_wm , & cursor_wm )) {
4178+ if (g4x_compute_wm0 (dev , 0 ,
4179+ & sandybridge_display_wm_info , latency ,
4180+ & sandybridge_cursor_wm_info , latency ,
4181+ & plane_wm , & cursor_wm )) {
42304182 I915_WRITE (WM0_PIPEA_ILK ,
42314183 (plane_wm << WM0_PIPE_PLANE_SHIFT ) | cursor_wm );
42324184 DRM_DEBUG_KMS ("FIFO watermarks For pipe A -"
@@ -4235,10 +4187,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
42354187 enabled |= 1 ;
42364188 }
42374189
4238- if (ironlake_compute_wm0 (dev , 1 ,
4239- & sandybridge_display_wm_info , latency ,
4240- & sandybridge_cursor_wm_info , latency ,
4241- & plane_wm , & cursor_wm )) {
4190+ if (g4x_compute_wm0 (dev , 1 ,
4191+ & sandybridge_display_wm_info , latency ,
4192+ & sandybridge_cursor_wm_info , latency ,
4193+ & plane_wm , & cursor_wm )) {
42424194 I915_WRITE (WM0_PIPEB_ILK ,
42434195 (plane_wm << WM0_PIPE_PLANE_SHIFT ) | cursor_wm );
42444196 DRM_DEBUG_KMS ("FIFO watermarks For pipe B -"
@@ -7675,6 +7627,7 @@ static void intel_init_display(struct drm_device *dev)
76757627 dev_priv -> display .update_wm = NULL ;
76767628 } else
76777629 dev_priv -> display .update_wm = pineview_update_wm ;
7630+ dev_priv -> display .init_clock_gating = gen3_init_clock_gating ;
76787631 } else if (IS_G4X (dev )) {
76797632 dev_priv -> display .update_wm = g4x_update_wm ;
76807633 dev_priv -> display .init_clock_gating = g4x_init_clock_gating ;
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