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[AMDGPU] Replace LegacyDA with Uniformity Analysis in AnnotateUniformValues
Reviewed By: sameerds Differential Revision: https://reviews.llvm.org/D144162
1 parent f35ac8a commit a783015

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2 files changed

+32
-22
lines changed

2 files changed

+32
-22
lines changed

llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@
1616
#include "Utils/AMDGPUBaseInfo.h"
1717
#include "Utils/AMDGPUMemoryUtils.h"
1818
#include "llvm/Analysis/AliasAnalysis.h"
19-
#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
2019
#include "llvm/Analysis/MemorySSA.h"
20+
#include "llvm/Analysis/UniformityAnalysis.h"
2121
#include "llvm/IR/InstVisitor.h"
2222
#include "llvm/InitializePasses.h"
2323

@@ -29,7 +29,7 @@ namespace {
2929

3030
class AMDGPUAnnotateUniformValues : public FunctionPass,
3131
public InstVisitor<AMDGPUAnnotateUniformValues> {
32-
LegacyDivergenceAnalysis *DA;
32+
UniformityInfo *UA;
3333
MemorySSA *MSSA;
3434
AliasAnalysis *AA;
3535
bool isEntryFunc;
@@ -55,7 +55,7 @@ class AMDGPUAnnotateUniformValues : public FunctionPass,
5555
return "AMDGPU Annotate Uniform Values";
5656
}
5757
void getAnalysisUsage(AnalysisUsage &AU) const override {
58-
AU.addRequired<LegacyDivergenceAnalysis>();
58+
AU.addRequired<UniformityInfoWrapperPass>();
5959
AU.addRequired<MemorySSAWrapperPass>();
6060
AU.addRequired<AAResultsWrapperPass>();
6161
AU.setPreservesAll();
@@ -69,7 +69,7 @@ class AMDGPUAnnotateUniformValues : public FunctionPass,
6969

7070
INITIALIZE_PASS_BEGIN(AMDGPUAnnotateUniformValues, DEBUG_TYPE,
7171
"Add AMDGPU uniform metadata", false, false)
72-
INITIALIZE_PASS_DEPENDENCY(LegacyDivergenceAnalysis)
72+
INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass)
7373
INITIALIZE_PASS_DEPENDENCY(MemorySSAWrapperPass)
7474
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
7575
INITIALIZE_PASS_END(AMDGPUAnnotateUniformValues, DEBUG_TYPE,
@@ -78,13 +78,13 @@ INITIALIZE_PASS_END(AMDGPUAnnotateUniformValues, DEBUG_TYPE,
7878
char AMDGPUAnnotateUniformValues::ID = 0;
7979

8080
void AMDGPUAnnotateUniformValues::visitBranchInst(BranchInst &I) {
81-
if (DA->isUniform(&I))
81+
if (UA->isUniform(&I))
8282
setUniformMetadata(&I);
8383
}
8484

8585
void AMDGPUAnnotateUniformValues::visitLoadInst(LoadInst &I) {
8686
Value *Ptr = I.getPointerOperand();
87-
if (!DA->isUniform(Ptr))
87+
if (!UA->isUniform(Ptr))
8888
return;
8989
Instruction *PtrI = dyn_cast<Instruction>(Ptr);
9090
if (PtrI)
@@ -108,7 +108,7 @@ bool AMDGPUAnnotateUniformValues::runOnFunction(Function &F) {
108108
if (skipFunction(F))
109109
return false;
110110

111-
DA = &getAnalysis<LegacyDivergenceAnalysis>();
111+
UA = &getAnalysis<UniformityInfoWrapperPass>().getUniformityInfo();
112112
MSSA = &getAnalysis<MemorySSAWrapperPass>().getMSSA();
113113
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
114114
isEntryFunc = AMDGPU::isEntryFunctionCC(F.getCallingConv());

llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

Lines changed: 25 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -79,13 +79,15 @@
7979
; GCN-O0-NEXT: Detect single entry single exit regions
8080
; GCN-O0-NEXT: Region Pass Manager
8181
; GCN-O0-NEXT: Structurize control flow
82-
; GCN-O0-NEXT: Post-Dominator Tree Construction
83-
; GCN-O0-NEXT: Natural Loop Information
84-
; GCN-O0-NEXT: Legacy Divergence Analysis
82+
; GCN-O0-NEXT: Cycle Info Analysis
83+
; GCN-O0-NEXT: Uniformity Analysis
8584
; GCN-O0-NEXT: Basic Alias Analysis (stateless AA impl)
8685
; GCN-O0-NEXT: Function Alias Analysis Results
8786
; GCN-O0-NEXT: Memory SSA
8887
; GCN-O0-NEXT: AMDGPU Annotate Uniform Values
88+
; GCN-O0-NEXT: Natural Loop Information
89+
; GCN-O0-NEXT: Post-Dominator Tree Construction
90+
; GCN-O0-NEXT: Legacy Divergence Analysis
8991
; GCN-O0-NEXT: SI annotate control flow
9092
; GCN-O0-NEXT: Post-Dominator Tree Construction
9193
; GCN-O0-NEXT: Legacy Divergence Analysis
@@ -273,13 +275,15 @@
273275
; GCN-O1-NEXT: Detect single entry single exit regions
274276
; GCN-O1-NEXT: Region Pass Manager
275277
; GCN-O1-NEXT: Structurize control flow
276-
; GCN-O1-NEXT: Post-Dominator Tree Construction
277-
; GCN-O1-NEXT: Natural Loop Information
278-
; GCN-O1-NEXT: Legacy Divergence Analysis
278+
; GCN-O1-NEXT: Cycle Info Analysis
279+
; GCN-O1-NEXT: Uniformity Analysis
279280
; GCN-O1-NEXT: Basic Alias Analysis (stateless AA impl)
280281
; GCN-O1-NEXT: Function Alias Analysis Results
281282
; GCN-O1-NEXT: Memory SSA
282283
; GCN-O1-NEXT: AMDGPU Annotate Uniform Values
284+
; GCN-O1-NEXT: Natural Loop Information
285+
; GCN-O1-NEXT: Post-Dominator Tree Construction
286+
; GCN-O1-NEXT: Legacy Divergence Analysis
283287
; GCN-O1-NEXT: SI annotate control flow
284288
; GCN-O1-NEXT: Post-Dominator Tree Construction
285289
; GCN-O1-NEXT: Legacy Divergence Analysis
@@ -571,13 +575,15 @@
571575
; GCN-O1-OPTS-NEXT: Detect single entry single exit regions
572576
; GCN-O1-OPTS-NEXT: Region Pass Manager
573577
; GCN-O1-OPTS-NEXT: Structurize control flow
574-
; GCN-O1-OPTS-NEXT: Post-Dominator Tree Construction
575-
; GCN-O1-OPTS-NEXT: Natural Loop Information
576-
; GCN-O1-OPTS-NEXT: Legacy Divergence Analysis
578+
; GCN-O1-OPTS-NEXT: Cycle Info Analysis
579+
; GCN-O1-OPTS-NEXT: Uniformity Analysis
577580
; GCN-O1-OPTS-NEXT: Basic Alias Analysis (stateless AA impl)
578581
; GCN-O1-OPTS-NEXT: Function Alias Analysis Results
579582
; GCN-O1-OPTS-NEXT: Memory SSA
580583
; GCN-O1-OPTS-NEXT: AMDGPU Annotate Uniform Values
584+
; GCN-O1-OPTS-NEXT: Natural Loop Information
585+
; GCN-O1-OPTS-NEXT: Post-Dominator Tree Construction
586+
; GCN-O1-OPTS-NEXT: Legacy Divergence Analysis
581587
; GCN-O1-OPTS-NEXT: SI annotate control flow
582588
; GCN-O1-OPTS-NEXT: Post-Dominator Tree Construction
583589
; GCN-O1-OPTS-NEXT: Legacy Divergence Analysis
@@ -877,13 +883,15 @@
877883
; GCN-O2-NEXT: Detect single entry single exit regions
878884
; GCN-O2-NEXT: Region Pass Manager
879885
; GCN-O2-NEXT: Structurize control flow
880-
; GCN-O2-NEXT: Post-Dominator Tree Construction
881-
; GCN-O2-NEXT: Natural Loop Information
882-
; GCN-O2-NEXT: Legacy Divergence Analysis
886+
; GCN-O2-NEXT: Cycle Info Analysis
887+
; GCN-O2-NEXT: Uniformity Analysis
883888
; GCN-O2-NEXT: Basic Alias Analysis (stateless AA impl)
884889
; GCN-O2-NEXT: Function Alias Analysis Results
885890
; GCN-O2-NEXT: Memory SSA
886891
; GCN-O2-NEXT: AMDGPU Annotate Uniform Values
892+
; GCN-O2-NEXT: Natural Loop Information
893+
; GCN-O2-NEXT: Post-Dominator Tree Construction
894+
; GCN-O2-NEXT: Legacy Divergence Analysis
887895
; GCN-O2-NEXT: SI annotate control flow
888896
; GCN-O2-NEXT: Post-Dominator Tree Construction
889897
; GCN-O2-NEXT: Legacy Divergence Analysis
@@ -1196,13 +1204,15 @@
11961204
; GCN-O3-NEXT: Detect single entry single exit regions
11971205
; GCN-O3-NEXT: Region Pass Manager
11981206
; GCN-O3-NEXT: Structurize control flow
1199-
; GCN-O3-NEXT: Post-Dominator Tree Construction
1200-
; GCN-O3-NEXT: Natural Loop Information
1201-
; GCN-O3-NEXT: Legacy Divergence Analysis
1207+
; GCN-O3-NEXT: Cycle Info Analysis
1208+
; GCN-O3-NEXT: Uniformity Analysis
12021209
; GCN-O3-NEXT: Basic Alias Analysis (stateless AA impl)
12031210
; GCN-O3-NEXT: Function Alias Analysis Results
12041211
; GCN-O3-NEXT: Memory SSA
12051212
; GCN-O3-NEXT: AMDGPU Annotate Uniform Values
1213+
; GCN-O3-NEXT: Natural Loop Information
1214+
; GCN-O3-NEXT: Post-Dominator Tree Construction
1215+
; GCN-O3-NEXT: Legacy Divergence Analysis
12061216
; GCN-O3-NEXT: SI annotate control flow
12071217
; GCN-O3-NEXT: Post-Dominator Tree Construction
12081218
; GCN-O3-NEXT: Legacy Divergence Analysis

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