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Commits on Oct 10, 2025

• [FIRRTL] Add LowerDomains pass (#8929)

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  seldridge

  authored
  822157a

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• [ImportVerilog][MooreToCore] Re-land Implement CHandle import and lowering

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  Scheremo

  committed
  28f7845

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• Revert unsquashed commits

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  Scheremo

  committed
  41ffa0b

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• Remove getDependentDialects

  Scheremo

  committed
  22db386

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• Mark ref<!llvm.ptr> issue as TODO

  Scheremo

  committed
  2598ae8

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• Raise error instead of dropping reference

  Scheremo

  committed
  4bca6de

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• Remove unneeded conversion

  Scheremo

  committed
  91dc526

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• [ImportVerilog][MooreToCore] Implement CHandle import and lowering

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  Scheremo

  committed
  c1f69c6

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• [Synth] Fix an incorrect canonicalization

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  uenoku

  committed
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Commits on Oct 9, 2025

• [ImportVerilog] Mention unsupported system call name in error

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  fabianschuiki

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  11ad8a8

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• [python][Synth] Provide fine-grained APIs for path queries (#9068)

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  uenoku

  authored
  f585d9a

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• [circt-lsp-server] Only enable unit tests if feature is enabled

  rwy7

  committed
  49a7020

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• [circt-lsp-verilog] "Debounce" onDidChange calls; update in worker

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  Scheremo

  committed
  8c1b0bd

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• [circt-verilog-lsp] Minimize project-scope File IO

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  Scheremo

  committed
  2198ac4

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• [Comb] Fix mux canonicalizers for non-signless-ints (#9071)

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  teqdruid

  authored
  1286a6c

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Commits on Oct 8, 2025

• [RTG] Add VirtualRegisterConfigAttr (#9059)

  maerhart

  authored
  6e13a7b

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• [ESI][Runtime] Search for backends via env var (#9070)

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  teqdruid

  authored
  a4abc68

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• [ESI] Various tweaks to cosim scripts (#9064)

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  mortbopet

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Commits on Oct 7, 2025

• [ESI] Fixed manifest override calculation

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  John Demme

  committed
  407c3d2

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• [CombToSynth] Compute Kogge-Stone prefix tree lazily in unsigned comparison lowering (#9050)

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  uenoku

  authored
  398cd5c

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• [PyCDE] Fixing dependency versions

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  John Demme

  committed
  5f5540e

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• [circt-verilog-lsp] Refactor VerilogIndex, add Package indexing

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  Scheremo

  committed
  b1323f7

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• [PyCDE][ESI] search only for Python Development.Module

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  John Demme

  committed
  5ee23d6

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• [RTG] Add isa.space operation (#9060)

  maerhart

  authored
  d322691

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• [RTG][EmbedValidationValuesPass] Allow ID duplicates if values match (#9061)

  maerhart

  authored
  4584498

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• [circt-synth] Pass a top module name to PrintLongestPathAnalysis

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  uenoku

  committed
  2027aeb

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Commits on Oct 6, 2025

• [ESI] ChannelMMIO: decrease MMIO space per client (#9062)

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  teqdruid

  authored
  fbc6bb4

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• [ESI] Fixing ESI integration tests

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  John Demme

  committed
  1833e2c

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• [circt-synth] Allow AIGER file to be an input file (#9054)

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  uenoku

  authored
  8a35dee

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• [CombToDatapath] Lower comb::SubOp (#9053)

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  uenoku

  authored
  187f4e8

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• [RTG] Implement getAsmResultNames for FixedRegisterOp (#9058)

  maerhart

  authored
  81ff229

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• [circt-verilog-lsp] Avoid recursing into other buffers when indexing

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  Scheremo

  committed
  e6674ee

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• [circt-verilog-lsp][NFC] Break out implementation classes

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  Scheremo

  committed
  741cbd6

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Commits on Oct 4, 2025

• [circt-verilog-lsp] Move to Slang's src mngr, drop LLVM src mngr (#9045)

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  Scheremo

  authored
  35af03c

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Commits on Oct 3, 2025

• [Comb][circt-synth] Implement BalanceMux pass for optimizing mux chains (#9044)

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  uenoku

  authored
  e589add

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