Skip to content

Commit 4957ffa

Browse files
rohit-numatorohit-numato
committed
Add skoll microblaze sample project
1 parent 64637fb commit 4957ffa

File tree

13 files changed

+2368
-0
lines changed

13 files changed

+2368
-0
lines changed

‎FPGA/skoll/NumatoVivadoBSB/README.md‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
2+
# How to install Numato Board Support Files for Vivado
3+
4+
In this current directory, there are folders named `neso` and `skoll`.
5+
6+
### Install
7+
* Copy these folders to `C:\Xilinx\Vivado\2015.2\data\boards\board_files` folder.
8+
* Done!
9+
10+
**Note:** Depending on your Vivado version and Vivado installation direcoty, your path might be different. Please change it as per your environment.

‎FPGA/skoll/NumatoVivadoBSB/neso/2.0/board.xml‎

Lines changed: 680 additions & 0 deletions
Large diffs are not rendered by default.

‎FPGA/skoll/NumatoVivadoBSB/neso/2.0/mig.prj‎

Lines changed: 134 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,134 @@
1+
<?xml version='1.0' encoding='UTF-8'?>
2+
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
3+
<Project NoOfControllers="1" >
4+
<ModuleName>design_1_mig_7series_0_0</ModuleName>
5+
<dci_inouts_inputs>1</dci_inouts_inputs>
6+
<dci_inputs>1</dci_inputs>
7+
<Debug_En>OFF</Debug_En>
8+
<DataDepth_En>1024</DataDepth_En>
9+
<LowPower_En>ON</LowPower_En>
10+
<XADC_En>Enabled</XADC_En>
11+
<TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
12+
<Version>2.3</Version>
13+
<SystemClock>No Buffer</SystemClock>
14+
<ReferenceClock>Use System Clock</ReferenceClock>
15+
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
16+
<BankSelectionFlag>FALSE</BankSelectionFlag>
17+
<InternalVref>1</InternalVref>
18+
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
19+
<dci_cascade>0</dci_cascade>
20+
<Controller number="0" >
21+
<MemoryDevice>DDR3_SDRAM/Components/MT41J128M16XX-125</MemoryDevice>
22+
<TimePeriod>2500</TimePeriod>
23+
<VccAuxIO>1.8V</VccAuxIO>
24+
<PHYRatio>4:1</PHYRatio>
25+
<InputClkFreq>200</InputClkFreq>
26+
<UIExtraClocks>0</UIExtraClocks>
27+
<MMCM_VCO>800</MMCM_VCO>
28+
<MMCMClkOut0> 1.000</MMCMClkOut0>
29+
<MMCMClkOut1>1</MMCMClkOut1>
30+
<MMCMClkOut2>1</MMCMClkOut2>
31+
<MMCMClkOut3>1</MMCMClkOut3>
32+
<MMCMClkOut4>1</MMCMClkOut4>
33+
<DataWidth>16</DataWidth>
34+
<DeepMemory>1</DeepMemory>
35+
<DataMask>1</DataMask>
36+
<ECC>Disabled</ECC>
37+
<Ordering>Normal</Ordering>
38+
<CustomPart>TRUE</CustomPart>
39+
<NewPartName>MT41J128M16-CUSTOM</NewPartName>
40+
<RowAddress>14</RowAddress>
41+
<ColAddress>10</ColAddress>
42+
<BankAddress>3</BankAddress>
43+
<MemoryVoltage>1.5V</MemoryVoltage>
44+
<C0_MEM_SIZE>268435456</C0_MEM_SIZE>
45+
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
46+
<PinSelection>
47+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M4" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
48+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R2" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
49+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K5" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
50+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
51+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K3" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
52+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P4" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
53+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M6" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
54+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
55+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L3" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
56+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P5" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
57+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M2" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
58+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N1" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
59+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L4" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
60+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N5" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
61+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P2" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
62+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P3" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
63+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R1" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
64+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L1" SLEW="" name="ddr3_cas_n" IN_TERM="" />
65+
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="L5" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
66+
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="L6" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
67+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M1" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
68+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K6" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
69+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T6" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
70+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
71+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R7" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
72+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V5" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
73+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
74+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V4" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
75+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T4" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
76+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V1" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
77+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T3" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
78+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V6" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
79+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R8" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
80+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U7" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
81+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V7" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
82+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
83+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
84+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R5" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
85+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T5" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
86+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U3" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
87+
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V9" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
88+
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
89+
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="U9" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
90+
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="U2" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
91+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M3" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
92+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N4" SLEW="" name="ddr3_ras_n" IN_TERM="" />
93+
<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="U8" SLEW="" name="ddr3_reset_n" IN_TERM="" />
94+
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N2" SLEW="" name="ddr3_we_n" IN_TERM="" />
95+
</PinSelection>
96+
<System_Control>
97+
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
98+
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
99+
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
100+
</System_Control>
101+
<TimingParameters>
102+
<Parameters twtr="8" trrd="8" trefi="7.8" tfaw="41" trtp="8" tcke="10" trfc="170" trp="14" tras="37" trcd="14" />
103+
</TimingParameters>
104+
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
105+
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
106+
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
107+
<mrMode name="Mode" >Normal</mrMode>
108+
<mrDllReset name="DLL Reset" >No</mrDllReset>
109+
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
110+
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
111+
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
112+
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
113+
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
114+
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>
115+
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
116+
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
117+
<emrDQS name="TDQS enable" >Enabled</emrDQS>
118+
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
119+
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
120+
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
121+
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
122+
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
123+
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
124+
<PortInterface>AXI</PortInterface>
125+
<AXIParameters>
126+
<C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
127+
<C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
128+
<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
129+
<C0_S_AXI_ID_WIDTH>3</C0_S_AXI_ID_WIDTH>
130+
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
131+
</AXIParameters>
132+
</Controller>
133+
134+
</Project>

‎FPGA/skoll/NumatoVivadoBSB/neso/2.0/neso_board.jpg‎

1.59 MB
Loading

0 commit comments

Comments
 (0)